actel_proasic3.sdc

JPEG_D IP Core Verilog crypted source

define_clock -name {clk} -period 36.5 -clockgroup default_clkgroup
define_input_delay  -default 3.0
define_output_delay -default 3.0
define_attribute  {clk} syn_noclockbuf {1}
define_attribute  {clk} syn_maxfan {100000}
define_global_attribute  {syn_ramstyle} {block_ram}