read_files_verilog.tcl

JPEG_D IP Core Verilog crypted source

#-----------------------------------------------------------------------------
#-- Project  : JPEG-D - Baseline JPEG Decoder
#--
#-- File     : read_files.tcl
#--
#-- Purpose  : Sample script for adding the RTL files for JPEG-D core in 
#-             a Synplify project. 
#--
#-- Created by ALMA Technologies S.A.
#-- Copyright (c) 2001-2008 Alma Technologies S.A.
#--
#-----------------------------------------------------------------------------
#-- Design Engineer        : Nikos Zervas
#-- Quality Engineer       : -
#-- Creation Date          : 25-Feb-08
#-- Last Modification Date : 25-Feb-08
#-- File history           :
#--      25-Feb-2008 (1.00) : Initial release
#-----------------------------------------------------------------------------
#-- Please review the terms of the license agreement before using this file.
#-- If you are not an authorized user, please destroy this source code file
#-- and notify Alma Technologies or CAST, Inc. immediately that you
#-- inadvertently received an unauthorized copy.
#-----------------------------------------------------------------------------

# Set relative path to RTL sources dirtectory
set ALMA_hdl_input_location ../../hdl/${ALMA_hdl_type}

# Library name set up
set ALMA_work_library jpeg_d

# Inlcude paths 
set_option -include_path "$ALMA_hdl_input_location/core/jpeg_e;$ALMA_hdl_input_location/core/dct"

# List of RTL files
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/regn.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/reg1.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/add.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/add_subtract.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/negative.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/mux_cos_constants.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/cos_constants.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/multiplier.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/shifter_in.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/row_to_column.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/dct_block_control_unit.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/dct_block.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/dct_control_unit.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/convert_io.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/rc_2d_dct.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/dct.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/dct/dct_full.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/huffman_e/shift_right.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/huffman_e/rle.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/huffman_e/h_tables_p.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/huffman_e/h_fifo.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/huffman_e/huffman_e.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/huffman_e/huffman_ep.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/huffman_e/rle_huffman_ep.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/fifo_mem.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/gen_pulse.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/stream_fifo_e.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/jpeg_e_core_cu.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/cfg_generator.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/dct_buffer.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/sof0_mask.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/markerparse_mems.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/jreg1.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/jregn.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/qmultiplier.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/delay.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/quantizer.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/datapath_e.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/jpeg_e_core.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/cu.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/markerparse.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/jpeg_e_common.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/jpeg_e_cu.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/mem_reg.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/reg_io_if.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/jpeg_e_no_mem.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/memories/dp_ram/dp_ram.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/memories/sp_ram/sp_ram.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/memories/cfg_ram.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/memories/dct_buffer_ram.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/memories/dct_transpose_ram.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/memories/dqt_ram.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/memories/huffman_fifo_ram.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/memories/huffman_ram.v"
add_file -verilog -lib $ALMA_work_library   "$ALMA_hdl_input_location/core/jpeg_e/jpeg_e.v"