📄 pll_d1.mdl
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RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Amplitude "-V"
Measurements "None"
}
Block {
BlockType Reference
Name "Ground"
Ports [0, 0, 0, 0, 0, 1]
Position [279, 370, 301, 395]
Orientation "down"
ShowName off
SourceBlock "powerlib/Elements/Ground"
SourceType "Ground"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
}
Block {
BlockType Reference
Name "Ground1"
Ports [0, 0, 0, 0, 0, 1]
Position [339, 120, 361, 145]
Orientation "down"
ShowName off
SourceBlock "powerlib/Elements/Ground"
SourceType "Ground"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
}
Block {
BlockType Reference
Name "Ideal Switch"
Ports [1, 0, 0, 0, 0, 1, 1]
Position [260, 55, 300, 110]
Orientation "down"
NamePlacement "alternate"
FontSize 10
SourceBlock "powerlib/Power\nElectronics/Ideal Switch"
SourceType "Ideal Switch"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ron "10"
Lon "0"
IC "0"
Rs "inf"
Cs "inf"
Measurements off
}
Block {
BlockType Reference
Name "Ideal Switch1"
Ports [1, 0, 0, 0, 0, 1, 1]
Position [260, 190, 300, 245]
Orientation "up"
FontSize 10
SourceBlock "powerlib/Power\nElectronics/Ideal Switch"
SourceType "Ideal Switch"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ron "10"
Lon "0"
IC "0"
Rs "inf"
Cs "inf"
Measurements off
}
Block {
BlockType Reference
Name "Voltage Measurement1"
Ports [0, 1, 0, 0, 0, 2]
Position [570, 153, 595, 177]
SourceBlock "powerlib/Measurements/Voltage Measurement"
SourceType "Voltage Measurement"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Block {
BlockType Outport
Name "Out1"
Position [615, 158, 645, 172]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "In2"
SrcPort 1
Points [0, -25]
DstBlock "Ideal Switch1"
DstPort 1
}
Line {
LineType "Connection"
SrcBlock "1.5nF"
SrcPort RConn1
Points [0, 0; 0, 25]
Branch {
ConnectType "DEST_SRC"
Points [-60, 0]
Branch {
ConnectType "DEST_DEST"
SrcBlock "3.9K, 6.8nF"
SrcPort RConn1
Points [0, 0; 0, 20]
}
Branch {
ConnectType "DEST_SRC"
Points [-150, 0]
Branch {
ConnectType "DEST_DEST"
SrcBlock "Ground"
SrcPort LConn1
Points [0, 0; 0, -10]
}
Branch {
ConnectType "DEST_SRC"
Points [0, -10]
DstBlock "DC Voltage Source3"
DstPort LConn1
}
}
}
Branch {
ConnectType "DEST_SRC"
Points [55, 0]
DstBlock "Voltage Measurement1"
DstPort LConn2
}
}
Line {
LineType "Connection"
Points [440, 160; 60, 0]
Branch {
ConnectType "SRC_DEST"
SrcBlock "1.5K"
SrcPort RConn1
Points [0, 0; 5, 0]
}
Branch {
ConnectType "SRC_SRC"
DstBlock "3.9K, 6.8nF"
DstPort LConn1
}
Branch {
ConnectType "DEST_SRC"
DstBlock "Voltage Measurement1"
DstPort LConn1
}
Branch {
ConnectType "DEST_SRC"
DstBlock "1.5nF"
DstPort LConn1
}
}
Line {
LineType "Connection"
SrcBlock "Ideal Switch"
SrcPort RConn1
Points [0, 0; 0, 35]
Branch {
ConnectType "DEST_SRC"
DstBlock "1.5K"
DstPort LConn1
}
Branch {
ConnectType "DEST_DEST"
SrcBlock "Ideal Switch1"
SrcPort RConn1
Points [0, -15]
}
}
Line {
LineType "Connection"
SrcBlock "Ideal Switch1"
SrcPort LConn1
Points [0, 10]
DstBlock "DC Voltage Source3"
DstPort RConn1
}
Line {
LineType "Connection"
SrcBlock "DC Voltage Source2"
SrcPort RConn1
Points [0, -5; -60, 0]
DstBlock "Ideal Switch"
DstPort LConn1
}
Line {
LineType "Connection"
SrcBlock "DC Voltage Source2"
SrcPort LConn1
Points [0, 0]
DstBlock "Ground1"
DstPort LConn1
}
Line {
SrcBlock "Voltage Measurement1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
Points [55, 0]
DstBlock "Ideal Switch"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "D phase/freq det. "
Ports [2, 2]
Position [110, 127, 155, 203]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "D phase/freq det. "
Location [207, 283, 722, 597]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "ref"
Position [30, 48, 60, 62]
IconDisplay "Port number"
Port {
PortNumber 1
Name "Reference"
PropagatedSignals "Input"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Inport
Name "var"
Position [15, 208, 45, 222]
Port "2"
IconDisplay "Port number"
Port {
PortNumber 1
Name "Variable"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Constant
Name "Constant"
Position [65, 95, 95, 125]
Value "1"
VectorParams1D on
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
}
Block {
BlockType Reference
Name "D Flip-Flop"
Ports [3, 2]
Position [205, 17, 250, 93]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
}
Block {
BlockType Reference
Name "D Flip-Flop1"
Ports [3, 2]
Position [200, 177, 245, 253]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [375, 112, 405, 143]
Orientation "left"
Operator "NAND"
}
Block {
BlockType Memory
Name "Memory1"
Position [275, 115, 305, 145]
Orientation "left"
}
Block {
BlockType Terminator
Name "Terminator"
Position [285, 65, 305, 85]
}
Block {
BlockType Terminator
Name "Terminator1"
Position [285, 225, 305, 245]
}
Block {
BlockType Outport
Name "U"
Position [460, 28, 490, 42]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "D"
Position [465, 188, 495, 202]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
Name "Variable"
Labels [0, 0]
SrcBlock "var"
SrcPort 1
DstBlock "D Flip-Flop1"
DstPort 2
}
Line {
SrcBlock "D Flip-Flop"
SrcPort 2
DstBlock "Terminator"
DstPort 1
}
Line {
SrcBlock "D Flip-Flop1"
SrcPort 2
DstBlock "Terminator1"
DstPort 1
}
Line {
Name "Reference"
Labels [0, 1]
SrcBlock "ref"
SrcPort 1
DstBlock "D Flip-Flop"
DstPort 2
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [35, 0]
Branch {
Points [0, -80]
DstBlock "D Flip-Flop"
DstPort 1
}
Branch {
Points [0, 80]
DstBlock "D Flip-Flop1"
DstPort 1
}
}
Line {
SrcBlock "Memory1"
SrcPort 1
Points [-90, 0]
Branch {
Points [0, -50]
DstBlock "D Flip-Flop"
DstPort 3
}
Branch {
Points [0, 110]
DstBlock "D Flip-Flop1"
DstPort 3
}
}
Line {
SrcBlock "D Flip-Flop"
SrcPort 1
Points [185, 0]
Branch {
DstBlock "U"
DstPort 1
}
Branch {
Points [-5, 0; 0, 85]
DstBlock "Logical\nOperator"
DstPort 1
}
}
Line {
SrcBlock "D Flip-Flop1"
SrcPort 1
Points [185, 0]
Branch {
DstBlock "D"
DstPort 1
}
Branch {
Points [0, -60]
DstBlock "Logical\nOperator"
DstPort 2
}
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
DstBlock "Memory1"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "Enabled\nScope"
Ports [1, 0, 1]
Position [610, 255, 655, 295]
TreatAsAtomicUnit on
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "Enabled\nScope"
Location [264, 311, 478, 529]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [25, 98, 55, 112]
IconDisplay "Port number"
}
Block {
BlockType EnablePort
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