📄 pll_d0_fncd.mdl
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}
Line {
SrcBlock "Relational\nOperator"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType Display
Name "Monitors k0...k4 "
Ports [1]
Position [190, 16, 275, 114]
Decimation "1"
Lockdown off
}
Block {
BlockType SubSystem
Name "More Info"
Ports []
Position [320, 350, 588, 366]
DropShadow on
ShowName off
AncestorBlock "rab_favorites/More Info"
OpenFcn "k0=1; k1=1; k2=1; k3=1; k4=1;"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
MaskDisplay "disp('double click to restore initial k0 k1 k2 "
"k3 k4 values')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "More Info"
Location [196, 208, 560, 421]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Annotation {
Name "This is an \"info\" block"
Position [179, 52]
UseDisplayTextAsClickCallback off
}
}
}
Block {
BlockType SubSystem
Name "More Info1"
Ports []
Position [320, 325, 588, 341]
DropShadow on
ShowName off
AncestorBlock "rab_favorites/More Info"
OpenFcn "k0=0.2623; k1=2.625; k2=2.54; k3=3.775; k4=2.20"
"2;"
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
MaskDisplay "disp('double click to restore OPTIMAL k0 k1 k2 "
"k3 k4 values')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "More Info1"
Location [196, 208, 560, 421]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Annotation {
Name "This is an \"info\" block"
Position [179, 52]
UseDisplayTextAsClickCallback off
}
}
}
Block {
BlockType Reference
Name "NCD Outport"
Ports [1]
Position [565, 20, 640, 100]
DropShadow on
SourceBlock "srolib/Signal Constraint"
SourceType "Signal Constraint"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
DialogPosition "[0.294791666666667 0.146666666666667 0.45 0.31]"
SaveIn "MAT file"
SaveAs "pll_d0_fncd_optim.mat"
LogID "SRO_DataLog_1"
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [510, 70, 540, 110]
Floating off
Location [36, 737, 452, 915]
Open off
NumInputPorts "1"
ZoomMode "yonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "0.00012"
YMin "-0.2"
YMax "1.4"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
LimitDataPoints off
SampleTime "0"
}
Block {
BlockType Sin
Name "Sine Wave"
Ports [0, 1]
Position [15, 140, 45, 170]
ShowName off
SineType "Time based"
Frequency "2*pi*(1e6)"
Phase "pi"
SampleTime "0"
Port {
PortNumber 1
Name "Input"
RTWStorageClass "Auto"
DataLoggingNameMode "SignalName"
}
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [190, 145, 210, 165]
ShowName off
IconShape "round"
Inputs "|-+"
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [445, 80, 465, 100]
ShowName off
IconShape "round"
Inputs "|++"
}
Block {
BlockType Reference
Name "Voltage-Controlled\nOscillator1"
Ports [1, 1]
Position [520, 132, 610, 178]
FontName "Arial"
SourceBlock "commsynccomp2/Continuous-Time\nVCO"
SourceType "Continuous-Time VCO"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ac "1"
Fc "4.9e6"
Kc "0.1e6"
Ph "pi*0.6"
}
Block {
BlockType Constant
Name "[k0 k1 k2 k3 k4]"
Position [110, 50, 150, 80]
Value "[k0, k1,k2,k3 k4]'"
VectorParams1D off
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
}
Block {
BlockType SubSystem
Name "phase/freq detector"
Ports [2, 2]
Position [130, 139, 170, 201]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "phase/freq detector"
Location [303, 221, 694, 521]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Inport
Name "ref"
Position [40, 58, 70, 72]
IconDisplay "Port number"
}
Block {
BlockType Inport
Name "var"
Position [40, 223, 70, 237]
Port "2"
IconDisplay "Port number"
}
Block {
BlockType Constant
Name "Constant"
Position [45, 140, 70, 160]
Value "1"
VectorParams1D on
SamplingMode "Sample based"
OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
}
Block {
BlockType Reference
Name "D Flip-Flop"
Ports [3, 2]
Position [130, 27, 175, 103]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
}
Block {
BlockType Reference
Name "D Flip-Flop1"
Ports [3, 2]
Position [125, 192, 170, 268]
SourceBlock "simulink_extras/Flip Flops/D Flip-Flop"
SourceType "DFlipFlop"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [195, 127, 225, 158]
Orientation "left"
Operator "NAND"
}
Block {
BlockType Memory
Name "Memory"
Position [130, 130, 160, 160]
Orientation "left"
}
Block {
BlockType Terminator
Name "T1"
Position [210, 75, 230, 95]
}
Block {
BlockType Terminator
Name "T2"
Position [195, 240, 215, 260]
}
Block {
BlockType Outport
Name "U"
Position [280, 203, 310, 217]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "D"
Position [280, 38, 310, 52]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "ref"
SrcPort 1
DstBlock "D Flip-Flop"
DstPort 2
}
Line {
SrcBlock "var"
SrcPort 1
DstBlock "D Flip-Flop1"
DstPort 2
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [0, 0; 15, 0]
Branch {
Points [0, -110]
DstBlock "D Flip-Flop"
DstPort 1
}
Branch {
Points [0, 55]
DstBlock "D Flip-Flop1"
DstPort 1
}
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
DstBlock "Memory"
DstPort 1
}
Line {
SrcBlock "Memory"
SrcPort 1
Points [0, 0; -20, 0]
Branch {
Points [0, -55]
DstBlock "D Flip-Flop"
DstPort 3
}
Branch {
Points [0, 110]
DstBlock "D Flip-Flop1"
DstPort 3
}
}
Line {
SrcBlock "D Flip-Flop"
SrcPort 1
Points [0, 0; 80, 0]
Branch {
Points [0, 90]
DstBlock "Logical\nOperator"
DstPort 1
}
Branch {
DstBlock "D"
DstPort 1
}
}
Line {
SrcBlock "D Flip-Flop1"
SrcPort 1
Points [0, 0; 85, 0]
Branch {
Points [0, -60]
DstBlock "Logical\nOperator"
DstPort 2
}
Branch {
DstBlock "U"
DstPort 1
}
}
Line {
SrcBlock "D Flip-Flop"
SrcPort 2
DstBlock "T1"
DstPort 1
}
Line {
SrcBlock "D Flip-Flop1"
SrcPort 2
DstBlock "T2"
DstPort 1
}
}
}
Line {
Name "Input"
SrcBlock "Sine Wave"
SrcPort 1
DstBlock "Make Square2"
DstPort 1
}
Line {
SrcBlock "Voltage-Controlled\nOscillator1"
SrcPort 1
Points [30, 0; 0, 60]
DstBlock "Make Square3"
DstPort 1
}
Line {
SrcBlock "Make Square2"
SrcPort 1
DstBlock "phase/freq detector"
DstPort 1
}
Line {
SrcBlock "phase/freq detector"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "phase/freq detector"
SrcPort 2
Points [25, 0]
DstBlock "Sum1"
DstPort 2
}
Line {
SrcBlock "Sum1"
SrcPort 1
DstBlock "Analog\nFilter Design1"
DstPort 1
}
Line {
SrcBlock "Make Square3"
SrcPort 1
DstBlock "Divide by N"
DstPort trigger
}
Line {
SrcBlock "Fout=N*Fr=5MHz"
SrcPort 1
DstBlock "Divide by N"
DstPort 1
}
Line {
SrcBlock "Divide by N"
SrcPort 1
Points [-55, 0; 0, -70]
DstBlock "phase/freq detector"
DstPort 2
}
Line {
SrcBlock "[k0 k1 k2 k3 k4]"
SrcPort 1
DstBlock "Monitors k0...k4 "
DstPort 1
}
Line {
SrcBlock "Loop Compensator"
SrcPort 1
DstBlock "Sum2"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [20, 0]
DstBlock "Sum2"
DstPort 2
}
Line {
SrcBlock "Sum2"
SrcPort 1
Points [5, 0; 5, 0]
Branch {
Points [0, -30]
DstBlock "NCD Outport"
DstPort 1
}
Branch {
DstBlock "Scope"
DstPort 1
}
Branch {
Points [0, 65]
DstBlock "Voltage-Controlled\nOscillator1"
DstPort 1
}
}
Line {
SrcBlock "Analog\nFilter Design1"
SrcPort 1
Points [10, 0]
Branch {
Points [0, -65]
DstBlock "Loop Compensator"
DstPort 1
}
Branch {
DstBlock "Gain"
DstPort 1
}
}
Annotation {
Position [58, 185]
UseDisplayTextAsClickCallback off
}
Annotation {
Name "1) run model, note poor loop settling time\n2) "
"Open NCD tool (dble click NCD Outport)\n3) click on Start Optimization in NCD"
" Tool "
Position [297, 34]
HorizontalAlignment "left"
UseDisplayTextAsClickCallback off
}
}
}
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