opb_ps2_dual_ref_v2_1_0.mpd

edk实现lcd通信,c语言和vhdl语言

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## Microprocessor Peripheral Definition
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BEGIN opb_ps2_dual_ref
OPTION IPTYPE=PERIPHERAL
OPTION  IMP_NETLIST=TRUE
OPTION  HDL=verilog


## Peripheral Options

OPTION SIM_MODELS = BEHAVIORAL:STRUCTURAL:TIMING

## Bus Interfaces
BUS_INTERFACE BUS = SOPB, BUS_STD = OPB, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xa9000000, MIN_SIZE=0x2000, BUS=SOPB
PARAMETER C_HIGHADDR = 0xa9001FFF, BUS=SOPB

## Ports
PORT OPB_BE = OPB_BE, DIR = IN, VEC = [0:3], BUS = SOPB
PORT IPIF_Rst = OPB_Rst, DIR = IN, BUS = SOPB
PORT OPB_Select = OPB_select, DIR = IN, BUS = SOPB
PORT OPB_DBus = OPB_DBus, DIR = IN, VEC = [0:31], BUS = SOPB
PORT OPB_Clk = "", DIR = IN, BUS = SOPB, SIGIS = CLK
PORT OPB_ABus = OPB_ABus, DIR = IN, VEC = [0:31], BUS = SOPB
PORT OPB_RNW = OPB_RNW, DIR = IN, BUS = SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = IN, BUS = SOPB
PORT Sys_Intr1 = "", DIR = OUT, SIGIS=INTERRUPT, LEVEL=HIGH
PORT Sys_Intr2 = "", DIR = OUT, SIGIS=INTERRUPT, LEVEL=HIGH
PORT Sln_XferAck = Sl_xferAck, DIR = OUT, BUS = SOPB
PORT Sln_DBus = Sl_DBus, DIR = OUT, VEC = [0:31], BUS = SOPB
PORT Sln_DBusEn = "", DIR = OUT
PORT Sln_errAck = Sl_errAck, DIR = OUT, BUS = SOPB
PORT Sln_retry = Sl_retry, DIR = OUT, BUS = SOPB
PORT Sln_toutSup = Sl_toutSup, DIR = OUT, BUS = SOPB
# PS2 #1 interface signal
PORT Clkin1 = "", DIR = IN
PORT Clkpd1 = "", DIR = OUT
PORT Rx1 = "", DIR = IN
PORT Txpd1 = "", DIR = OUT
# PS2 #2 interface signal
PORT Clkin2 = "", DIR = IN
PORT Clkpd2 = "", DIR = OUT
PORT Rx2 = "", DIR = IN
PORT Txpd2 = "", DIR = OUT

END