user_logic.vhd

edk实现lcd通信,c语言和vhdl语言

------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.            **
-- **                                                                       **
-- ** Xilinx, Inc.                                                          **
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-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
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-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
-- ** FOR A PARTICULAR PURPOSE.                                             **
-- **                                                                       **
-- ** YOU MAY COPY AND MODIFY THESE FILES FOR YOUR OWN INTERNAL USE SOLELY  **
-- ** WITH XILINX PROGRAMMABLE LOGIC DEVICES AND XILINX EDK SYSTEM OR       **
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-- ** UNLESS THEY ARE DISTRIBUTED IN XILINX PROGRAMMABLE LOGIC DEVICES.     **
-- **                                                                       **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename:          user_logic.vhd
-- Version:           1.00.a
-- Description:       User logic.
-- Date:              Sat Apr 01 22:37:13 2006 (by Create and Import Peripheral Wizard)
-- VHDL Standard:     VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
--   active low signals:                    "*_n"
--   clock signals:                         "clk", "clk_div#", "clk_#x"
--   reset signals:                         "rst", "rst_n"
--   generics:                              "C_*"
--   user defined types:                    "*_TYPE"
--   state machine next state:              "*_ns"
--   state machine current state:           "*_cs"
--   combinatorial signals:                 "*_com"
--   pipelined or register delay signals:   "*_d#"
--   counter signals:                       "*cnt*"
--   clock enable signals:                  "*_ce"
--   internal version of output port:       "*_i"
--   device pins:                           "*_pin"
--   ports:                                 "- Names begin with Uppercase"
--   processes:                             "*_PROCESS"
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------

-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------

--USER libraries added here

------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
--   C_DWIDTH                     -- User logic data bus width
--   C_NUM_CE                     -- User logic chip enable bus width
--
-- Definition of Ports:
--   Bus2IP_Clk                   -- Bus to IP clock
--   Bus2IP_Reset                 -- Bus to IP reset
--   Bus2IP_Data                  -- Bus to IP data bus for user logic
--   Bus2IP_BE                    -- Bus to IP byte enables for user logic
--   Bus2IP_RdCE                  -- Bus to IP read chip enable for user logic
--   Bus2IP_WrCE                  -- Bus to IP write chip enable for user logic
--   IP2Bus_Data                  -- IP to Bus data bus for user logic
--   IP2Bus_Ack                   -- IP to Bus acknowledgement
--   IP2Bus_Retry                 -- IP to Bus retry response
--   IP2Bus_Error                 -- IP to Bus error response
--   IP2Bus_ToutSup               -- IP to Bus timeout suppress
--   IP2Bus_PostedWrInh           -- IP to Bus posted write inhibit
------------------------------------------------------------------------------

entity user_logic is
  generic
  (
    -- ADD USER GENERICS BELOW THIS LINE ---------------
    --USER generics added here
    -- ADD USER GENERICS ABOVE THIS LINE ---------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol parameters, do not add to or delete
    C_DWIDTH                       : integer              := 32;
    C_NUM_CE                       : integer              := 1
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
  port
  (
    -- ADD USER PORTS BELOW THIS LINE ------------------
    		lcd_data		   			: out std_logic_vector (0 to 7);
    		lcd_en 	 					: out std_logic;
	 	lcd_rs	 	 				: out std_logic;
    		lcd_rw			  			: out std_logic;
    -- ADD USER PORTS ABOVE THIS LINE ------------------

    -- DO NOT EDIT BELOW THIS LINE ---------------------
    -- Bus protocol ports, do not add to or delete
    Bus2IP_Clk                     : in  std_logic;
    Bus2IP_Reset                   : in  std_logic;
    Bus2IP_Data                    : in  std_logic_vector(0 to C_DWIDTH-1);
    Bus2IP_BE                      : in  std_logic_vector(0 to C_DWIDTH/8-1);
    Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_CE-1);
    IP2Bus_Data                    : out std_logic_vector(0 to C_DWIDTH-1);
    IP2Bus_Ack                     : out std_logic;
    IP2Bus_Retry                   : out std_logic;
    IP2Bus_Error                   : out std_logic;
    IP2Bus_ToutSup                 : out std_logic;
    IP2Bus_PostedWrInh             : out std_logic
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
  );
end entity user_logic;

------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------

architecture IMP of user_logic is

	----------------------------------------
	-- User logic S/W accessible registers
	----------------------------------------
	signal reg0	: std_logic_vector(0 to C_DWIDTH-1);
	signal Bus2IP_RdReq	: std_logic;
	signal Bus2IP_WrReq	: std_logic;
	signal Bus2IP_WrCE_delay	: std_logic;
	signal Bus2IP_RdCE_delay	: std_logic;


signal	IP2Bus_WrAck_i				: std_logic;
signal	IP2Bus_RdAck_i				: std_logic;
signal	ack_count		 			: std_logic_vector (0 to 5);
signal	ack_count_tc		 		: std_logic;


begin


--	reg0(22)		MSB		lcd_rs signal
--	reg0(23)				lcd_rw signal
--	reg0(24)				lcd data bit 0
--	reg0(25)				lcd data bit 1
--	reg0(26)				lcd data bit 2
--	reg0(27)				lcd data bit 3
--	reg0(28)				lcd data bit 4
--	reg0(29)				lcd data bit 5
--	reg0(30)				lcd data bit 6
--	reg0(31)		LSB		lcd data bit 7
--
--	Please keep in mind that lcd data bit 0 is the MSB of the lcd data bus and it must
--	be connected to the bit 7 of the lcd panel on the board.


	REQUEST_PROC : process( Bus2IP_Clk ) is
	begin
		if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
			if Bus2IP_Reset = '1' then
				Bus2IP_WrCE_delay <= '1';
				Bus2IP_RdCE_delay <= '1';
			else
				Bus2IP_WrCE_delay <= not Bus2IP_WrCE(0);
				Bus2IP_RdCE_delay <= not Bus2IP_RdCE(0);
			end if;
		end if;
	end process REQUEST_PROC;

	Bus2IP_RdReq	<= Bus2IP_RdCE(0) and Bus2IP_RdCE_delay;
	Bus2IP_WrReq	<= Bus2IP_WrCE(0) and Bus2IP_WrCE_delay;



	----------------------------------------
	-- User logic S/W accessible registers write example
	----------------------------------------
	REG_WRITE_PROC : process( Bus2IP_Clk ) is
	begin
		if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
			if Bus2IP_Reset = '1' then
				reg0 <= (others => '0');
			elsif (Bus2IP_WrCE(0) = '1' and Bus2IP_WrReq = '1') then
					reg0 <= Bus2IP_Data;
			end if;
		end if;
	end process REG_WRITE_PROC;


	----------------------------------------
	-- User logic S/W accessible registers read example
	----------------------------------------
	REG_READ_PROC : process( Bus2IP_RdCE, reg0 ) is
	begin
		if (Bus2IP_RdCE(0) = '1') then
			IP2Bus_Data <= reg0;
		else
			IP2Bus_Data <= (others => '0');
		end if;
	end process REG_READ_PROC;





--	The following implements a 6-bit counter that is used during write cycles to the
--	lcd. At the beginning of the write cycle, the counter is loaded with 0x3f and then
--	it is decremented on every rising edge of the clock. A terminal count called
--	ack_count_tc is generated when the count reaches 0x03.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		ack_count <= (others => '0');
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		if (Bus2IP_WrReq = '1') then
			ack_count <= (others => '1');
		elsif (Bus2IP_WrCE(0) = '1') then
			ack_count <= ack_count - 1;
		end if;
	end if;
end process;


process (ack_count)
begin
	if (ack_count = "000011") then
		ack_count_tc <= '1';
	else
		ack_count_tc <= '0';
	end if;
end process;




--	The following uses the ack_count_tc signal to generate the OPB acknowledge signal
--	for the write cycle.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		IP2Bus_WrAck_i <= '0';
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		IP2Bus_WrAck_i <= ack_count_tc;
	end if;
end process;




--	The following uses the read request from the OPB to generate the OPB acknowledge
--	signal for the read cycle. The core terminates a read cycle in 2 clocks and returns
--	zeros on the data bus.

process (Bus2IP_Clk, Bus2IP_Reset)
begin
	if (Bus2IP_Reset = '1') then
		IP2Bus_RdAck_i <= '0';
	elsif (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
		if (Bus2IP_RdCE(0) = '1') then
			IP2Bus_RdAck_i <= Bus2IP_RdReq;
		end if;
	end if;
end process;




--	Various lcd interface and ipif user side signals are set in the following section.
--	The MSB of the ack_count counter is used to generate the enable signal (lcd_en) to
--	the lcd panel.

IP2Bus_Ack 					<= IP2Bus_WrAck_i or IP2Bus_RdAck_i;
IP2Bus_Error 				<= '0';
IP2Bus_Retry 				<= '0';
IP2Bus_ToutSup 				<= Bus2IP_WrCE(0) or Bus2IP_RdCE(0) ;
IP2Bus_PostedWrInh			<= '1';

lcd_rs					<= reg0(22);
lcd_rw					<= reg0(23);
lcd_data					<= reg0(24 to 31);
lcd_en					<= ack_count(0);

end IMP;