my_lcd.cli

edk实现lcd通信,c语言和vhdl语言

NewProject(F:\powerpc\Board\basic\pcores\my_lcd_v1_00_a\devl\projnav\my_lcd.npl)
SetProperty(Top-Level Module Type, HDL)
SetProperty(Synthesis Tool, XST (VHDL/Verilog))
SetProperty(Simulator, ModelSim)
SetPreference(PathType, Absolute)
AddLibrary(my_lcd_v1_00_a, F:\powerpc\Board\basic\pcores, TRUE)
AddSource(F:\powerpc\Board\basic\pcores\my_lcd_v1_00_a\hdl\vhdl\my_lcd.vhd, VHDL Design File)
MoveToLibrary(F:\powerpc\Board\basic\pcores\my_lcd_v1_00_a\hdl\vhdl\my_lcd.vhd, my_lcd_v1_00_a)
AddSource(F:\powerpc\Board\basic\pcores\my_lcd_v1_00_a\hdl\vhdl\user_logic.vhd, VHDL Design File)
MoveToLibrary(F:\powerpc\Board\basic\pcores\my_lcd_v1_00_a\hdl\vhdl\user_logic.vhd, my_lcd_v1_00_a)
AddLibrary(proc_common_v2_00_a, E:\EDK\hw\XilinxProcessorIPLib\pcores, TRUE)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\proc_common_pkg.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\proc_common_pkg.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\family.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\family.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_muxcy.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_muxcy.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_gate.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\or_gate.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter_bit.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter_bit.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\counter.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\inferred_lut4.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\inferred_lut4.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl_fifo2.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl_fifo2.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_bit.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_bit.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_top.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_counter_top.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter_top.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_occ_counter_top.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder_bit.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder_bit.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_adder.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_dpram_select.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pf_dpram_select.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl16_fifo.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\srl16_fifo.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pselect.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\pselect.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\valid_be.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\valid_be.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ld_arith_reg.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ld_arith_reg.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\mux_onehot.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\mux_onehot.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\down_counter.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\down_counter.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_pkg.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_pkg.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_steer.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\ipif_steer.vhd, proc_common_v2_00_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\direct_path_cntr_ai.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v2_00_a\hdl\vhdl\direct_path_cntr_ai.vhd, proc_common_v2_00_a)
AddLibrary(interrupt_control_v1_00_a, E:\EDK\hw\XilinxProcessorIPLib\pcores, TRUE)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v1_00_a\hdl\vhdl\interrupt_control.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v1_00_a\hdl\vhdl\interrupt_control.vhd, interrupt_control_v1_00_a)
AddLibrary(wrpfifo_v1_01_b, E:\EDK\hw\XilinxProcessorIPLib\pcores, TRUE)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\pf_dly1_mux.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\pf_dly1_mux.vhd, wrpfifo_v1_01_b)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\ipif_control_wr.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\ipif_control_wr.vhd, wrpfifo_v1_01_b)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_dp_cntl.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_dp_cntl.vhd, wrpfifo_v1_01_b)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_top.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\wrpfifo_v1_01_b\hdl\vhdl\wrpfifo_top.vhd, wrpfifo_v1_01_b)
AddLibrary(rdpfifo_v1_01_b, E:\EDK\hw\XilinxProcessorIPLib\pcores, TRUE)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\ipif_control_rd.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\ipif_control_rd.vhd, rdpfifo_v1_01_b)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_dp_cntl.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_dp_cntl.vhd, rdpfifo_v1_01_b)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_top.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\rdpfifo_v1_01_b\hdl\vhdl\rdpfifo_top.vhd, rdpfifo_v1_01_b)
AddLibrary(opb_ipif_v3_01_a, E:\EDK\hw\XilinxProcessorIPLib\pcores, TRUE)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\reset_mir.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\reset_mir.vhd, opb_ipif_v3_01_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr.vhd, opb_ipif_v3_01_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_flex_addr_cntr.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_flex_addr_cntr.vhd, opb_ipif_v3_01_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr_reg.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\brst_addr_cntr_reg.vhd, opb_ipif_v3_01_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_be_gen.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_be_gen.vhd, opb_ipif_v3_01_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\srl_fifo3.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\srl_fifo3.vhd, opb_ipif_v3_01_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\write_buffer.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\write_buffer.vhd, opb_ipif_v3_01_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_bam.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_bam.vhd, opb_ipif_v3_01_a)
AddSource(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_ipif.vhd, VHDL Design File)
MoveToLibrary(E:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v3_01_a\hdl\vhdl\opb_ipif.vhd, opb_ipif_v3_01_a)
CloseProject()