up_system_info.pm

基于Avalon的SDRAM控制器IP核

# +----------------------------------------------------------------------------+
# | Copyright (C)2001-2006 Altera Corporation                                  |
# |  Any megafunction design, and related net list (encrypted or decrypted),   |
# |  support information, device programming or simulation file, and any other |
# |  associated documentation or information provided by Altera or a partner   |
# |  under Altera's Megafunction Partnership Program may be used only to       |
# |  program PLD devices (but not masked PLD devices) from Altera.  Any other  |
# |  use of such megafunction design, net list, support information, device    |
# |  programming or simulation file, or any other related documentation or     |
# |  information is prohibited for any other purpose, including, but not       |
# |  limited to modification, reverse engineering, de-compiling, or use with   |
# |  any other silicon devices, unless such use is explicitly licensed under   |
# |  a separate agreement with Altera or a megafunction partner.  Title to     |
# |  the intellectual property, including patents, copyrights, trademarks,     |
# |  trade secrets, or maskworks, embodied in any such megafunction design,    |
# |  net list, support information, device programming or simulation file, or  |
# |  any other related documentation or information provided by Altera or a    |
# |  megafunction partner, remains with Altera, the megafunction partner, or   |
# |  their respective licensors.  No other licenses, including any licenses    |
# |  needed under any third party's intellectual property, are provided herein.|
# |  Copying or modifying any file, or portion thereof, to which this notice   |
# |  is attached violates this copyright.                                      |
# +----------------------------------------------------------------------------+




# +----------------------------------------------------------------------------+
# | file: UP_System_Info.pm                                                    |
# |                                                                            |
# | This SOPC Builder Generator program is provided by                         |
# | Altera's University Program.                                               |
# |                                                                            |
# | Its purpose is to construct the HDL files for                              |
# | a particular instance of a particular University                           |
# | Program SOPC Builder peripheral.                                           |
# |                                                                            |
# | version: 0.3                                                               |
# |                                                                            |
# +----------------------------------------------------------------------------+

package UP_System_Info;
use Exporter;


@ISA = Exporter;
@EXPORT = qw(
	initialize_system_info
	get_ip_core_directory
	get_ip_core_target_name
	get_system_directory
	generator_print_verbose

	get_module_ptf
	get_module_ptf_from_system_ptf
);


use strict;
use format_conversion_utils;
use ptf_parse;


my $generator_args = {
			system_directory => "",
			system_name => "",
			system_ptf => "",

			ip_core_directory => "",
			ip_core_target_name => "",

			hdl_langauge => "",

			verbose => 0,
};

my $hdl_file = {
		module_info => {
			name => 0,
			description => "",
		},
    };

sub initialize_system_info
{
#	print "Initializing System Info\n";

	parse_generator_arguments();

	return 1;
}

sub get_ip_core_directory
{
	return $generator_args->{ip_core_directory};
}

sub get_ip_core_target_name
{
	return $generator_args->{ip_core_target_name};
}

sub get_system_directory
{
	return $generator_args->{system_directory};
}

sub get_module_ptf
{
	return &new_ptf_from_file($generator_args->{ip_core_directory}."/class.ptf");
}

sub get_module_ptf_from_system_ptf
{
	return &get_child_by_path($generator_args->{system_ptf}, "SYSTEM $generator_args->{system_name}/MODULE $generator_args->{ip_core_target_name}");
}


sub generator_print_verbose
{
	my ($info) = (@_);

	if($generator_args->{verbose} eq 1){
		print("UP_IP_Core_Generator.pm: ".$info."\n");
	}
}

sub parse_generator_arguments
{

	push(@ARGV,"--verbose=1") if 0;
	my %args = fcu_parse_args(@ARGV);

	# Print out all the arguments
	if(0)
	{
		print("  UP_IP_Core_Generator.pm arguments:\n");
		foreach my $key (sort(keys(%args)))
		{
			print("    --$key = $args{$key} \n");
		}
	}

	$generator_args->{system_directory} = fcu_get_switch(\%args,"system_directory");
	$generator_args->{system_name} =  fcu_get_switch(\%args,"system_name");
	$generator_args->{system_ptf} = new_ptf_from_file($generator_args->{system_directory}."/".$generator_args->{system_name}.".ptf");

	$generator_args->{ip_core_directory} = fcu_get_switch(\%args,"module_lib_dir");
	$generator_args->{ip_core_target_name} = fcu_get_switch(\%args,"target_module_name");

	$generator_args->{hdl_langauge} =  get_data_by_path($generator_args->{system_ptf}, 
				"SYSTEM $generator_args->{system_name}/WIZARD_SCRIPT_ARGUMENTS/hdl_language");

	$generator_args->{verbose} = fcu_get_switch(\%args,"verbose");
}


# End with success

return 1;

# end of file