class.ptf

基于Avalon的SDRAM控制器IP核

#
# This class.ptf file built by Component Editor
# 2006.10.29.18:58:29
#
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CLASS altera_up_avalon_sram
{
	CB_GENERATOR 
	{
		HDL_FILES 
		{
			FILE 
			{
				use_in_simulation	= "1";
				use_in_synthesis	= "1";
				type				= "verilog";
				filepath			= "hdl/Altera_UP_Avalon_SRAM.v";
			}
		}
		top_module_name	= "Altera_UP_Avalon_SRAM.v:Altera_UP_Avalon_SRAM";
		emit_system_h	= "0";
		LIBRARIES 
		{
		}
	}
   MODULE_DEFAULTS global_signals
   {
      class = "altera_up_avalon_sram";
      class_version = "6.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module	= "1";
         Has_Clock						= "1";
         Default_Module_Name			= "sram";
         Top_Level_Ports_Are_Enumerated	= "1";
      }
      COMPONENT_BUILDER 
      {
         GLS_SETTINGS 
         {
         }
      }
      PORT_WIRING 
      {
         PORT clk
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "clk";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT reset
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "reset";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         hdl_parameters 
         {
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
         }
      }
      SLAVE avalon_sram_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "1";
            Has_Clock = "0";
            Address_Width = "18";
            Address_Alignment = "dynamic";
            Data_Width = "16";
            Has_Base_Address = "1";
            Has_IRQ = "0";
            Setup_Time = "0cycles";
            Hold_Time = "0cycles";
            Read_Wait_States = "0cycles";
            Write_Wait_States = "0cycles";
            Read_Latency = "2";
            Maximum_Pending_Read_Transactions = "0";
            Active_CS_Through_Read_Latency = "0";
            Is_Printable_Device = "0";
            Is_Memory_Device = "1";
            Is_Readable = "1";
            Is_Writable = "1";
            Minimum_Uninterrupted_Run_Length = "1";
         }
         COMPONENT_BUILDER 
         {
            AVS_SETTINGS 
            {
               Setup_Value = "0";
               Read_Wait_Value = "0";
               Write_Wait_Value = "0";
               Hold_Value = "0";
               Timing_Units = "cycles";
               Read_Latency_Value = "2";
               Minimum_Arbitration_Shares = "1";
               Active_CS_Through_Read_Latency = "0";
               Max_Pending_Read_Transactions_Value = "1";
               Address_Alignment = "dynamic";
               Is_Printable_Device = "0";
               Interleave_Bursts = "0";
               interface_name = "Avalon Slave";
               external_wait = "0";
               Is_Memory_Device = "1";
            }
         }
         PORT_WIRING 
         {
            PORT address
            {
               width = "18";
               width_expression = "";
               direction = "input";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT byteenable
            {
               width = "2";
               width_expression = "";
               direction = "input";
               type = "byteenable";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT chipselect
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "chipselect";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT read
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "read";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT write
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "write";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT writedata
            {
               width = "16";
               width_expression = "";
               direction = "input";
               type = "writedata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_DQ
            {
               width = "16";
               width_expression = "";
               direction = "inout";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_ADDR
            {
               width = "18";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_LB_N
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_UB_N
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_CE_N
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_OE_N
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT SRAM_WE_N
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT readdata
            {
               width = "16";
               width_expression = "";
               direction = "output";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
   }
	USER_INTERFACE 
	{
		USER_LABELS 
		{
			name		= "SRAM";
			technology	= "University Program DE1 Board,University Program DE2 Board";
		}
		LINKS
		{
			LINK datasheet
			{
				title = "Data Sheet";
				url = "../doc/SRAM_Controller.pdf";
			}
		}
		WIZARD_UI add_edit_wizard_ui
		{
			title = "SRAM - {{ $MOD }}";
			CONTEXT 
			{
				H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
				M = "";
				SBI_global_signals		= "SYSTEM_BUILDER_INFO";
				SBI_avalon_sram_slave	= "SLAVE avalon_sram_slave/SYSTEM_BUILDER_INFO";
			}
			GROUP
			{
				align = "left";
				layout = "vertical";
				TEXT 
				{
					title = "SRAM Controller";
				}
				TEXT 
				{
					title = "DE1 and DE2 Development and Education Boards";
				}
				TEXT 
				{
					title = "Total memory:  512 KBytes";
				}
				TEXT 
				{
					title = "Memory Format: 256K x 16Bit words";
				}
			}
		}
	}
	ASSOCIATED_FILES 
	{
		Add_Program			= "add_edit_wizard_ui";
		Edit_Program		= "add_edit_wizard_ui";
		Generator_Program	= "UP_IP_Core_Generator.pl";
	}
}