up_ip_core_generator.pl

基于Avalon的SDRAM控制器IP核

# +----------------------------------------------------------------------------+
# | Copyright (C)2001-2006 Altera Corporation                                  |
# |  Any megafunction design, and related net list (encrypted or decrypted),   |
# |  support information, device programming or simulation file, and any other |
# |  associated documentation or information provided by Altera or a partner   |
# |  under Altera's Megafunction Partnership Program may be used only to       |
# |  program PLD devices (but not masked PLD devices) from Altera.  Any other  |
# |  use of such megafunction design, net list, support information, device    |
# |  programming or simulation file, or any other related documentation or     |
# |  information is prohibited for any other purpose, including, but not       |
# |  limited to modification, reverse engineering, de-compiling, or use with   |
# |  any other silicon devices, unless such use is explicitly licensed under   |
# |  a separate agreement with Altera or a megafunction partner.  Title to     |
# |  the intellectual property, including patents, copyrights, trademarks,     |
# |  trade secrets, or maskworks, embodied in any such megafunction design,    |
# |  net list, support information, device programming or simulation file, or  |
# |  any other related documentation or information provided by Altera or a    |
# |  megafunction partner, remains with Altera, the megafunction partner, or   |
# |  their respective licensors.  No other licenses, including any licenses    |
# |  needed under any third party's intellectual property, are provided herein.|
# |  Copying or modifying any file, or portion thereof, to which this notice   |
# |  is attached violates this copyright.                                      |
# +----------------------------------------------------------------------------+




# +----------------------------------------------------------------------------+
# | file: UP_IP_Core_Generator.pl                                              |
# |                                                                            |
# | This SOPC Builder Generator program is provided by                         |
# | Altera's University Program.                                               |
# |                                                                            |
# | Its purpose is to construct the HDL files for a particular instance of a   |
# | particular University Program SOPC Builder peripheral.                     |
# |                                                                            |
# | version: 0.3                                                               |
# |                                                                            |
# +----------------------------------------------------------------------------+

use strict;
use UP_System_Info;
use UP_PTF_Parser;
use UP_HDL_Parser;
use UP_HDL_Writer;
use UP_Extras;

sub main
{
	my $error;
	my $module_name;
	my @hdl_file;

#	print "Running the A/V Config Generator!!\n";

	($error) = initialize_system_info();
	&ribbit ($error) if ($error != 1);
	($error) = initialize_ptf_parser();
	&ribbit ($error) if ($error != 1);

	my $hdl_file_count = get_num_hdl_files();

	for (my $i = 0; $i < $hdl_file_count; $i++)
	{
		($error, $module_name, @hdl_file) = parse_hdl_file(get_hdl_filename($i), check_top_level_module_flag($i));
		&ribbit ($error) if ($error != 1);
		($error) = write_hdl_file($module_name, @hdl_file);
		&ribbit ($error) if ($error != 1);
	}
	
	($error) = copy_additional_files();
	&ribbit ($error) if ($error != 1);

    exit (0);
}

$| = 1;  # always polite to flush.
main()

# end of file