fft1.txt

a nice text file explaining the fft

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

PACKAGE untitled_pkg IS
TYPE vector_of_std_logic_vector16 IS ARRAY (NATURAL RANGE <>) OF INTEGER;
END untitled_pkg;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE work.untitled_pkg.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Hussain is

generic(N:integer:=8;
log:integer:=3);

port(x:in vector_of_std_logic_vector16(0 TO 7);
clk:in std_logic;
yut vector_of_std_logic_vector16(0 TO 7));
end Hussain;

architecture Behavioral of Hussain is

begin

top: process(clk)
variable b,s,k,h,temp3,temp4:integer;
variable temp:vector_of_std_logic_vector16(0 TO 7);
variable temp1,temp2,w:integer;

begin

If rising_edge(clk)then

temp:=x;


loop1: for l in 1 to log loop
b:=N/(2**l);
s:=N/(2*b);

loop2: for R in 1 to s loop
h:=0; k:=0;
loop3: for n in 0 to (b-1) loop


wRom: case k is

when 0 => w := 2;
when 1 => w := 3;
when 2 => w := 4;
when 3 => w := 5;
when others => null;
end case;

temp1:=temp(n+h)+temp(n+h+(b/2));
temp2:=w*(temp(n+h)-temp(n+h+(b/2)));
temp(n+h):=temp1;
temp(n+h+(b/2)):=temp2;
temp3:=k+s;
k:=temp3;
End loop;
temp4:=h+(2*b);
h:=temp4;
End loop;
End loop;
End IF;
Y<=temp;
End process;

end Behavioral;