testbench_syn.vhd

本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use work.Signal_Model_pkg.all;

ENTITY testbench_syn IS
--generic(
--	OUT_WIDTH : natural := 24
--);
--port(
--	clk	: in std_logic;
--	ena	: in std_logic;
--	phase1 	: out signed(OUT_WIDTH-1 downto 0);
--	ready1	: out std_logic;
--	phase2 	: out signed(OUT_WIDTH-1 downto 0);
--	ready2	: out std_logic;
--);
END testbench_syn;

ARCHITECTURE tb_cordic OF testbench_syn IS

component r2p_corproc is
        generic(
                WIDTH           : natural := 16;           -- Width of input
                XY_WIDTH        : natural := 20;           -- Width of X and Y-vector, must be greater than WIDTH!
                Z_WIDTH         : natural := 20;           -- Width of Z-vector, must be greater than OUT_WIDTH
                PIPELENGTH      : natural := 15;           -- number of cascades, affects precision
                OUT_WIDTH	: natural := 12            -- output width, must be smaller than Z_WIDTH
        );
        port(
                clk     : in std_logic;
                ena     : in std_logic;                    -- global synchronous enable with '1' as actived
                Xin     : in signed(WIDTH-1 downto 0);     -- value of denominator
                Yin     : in signed(WIDTH-1 downto 0);     -- value of numerator
                rdy     : out std_logic;                   -- ready Signal, '1' indicates data available on output 
                Aout    : out signed(OUT_WIDTH-1 downto 0)   -- Arctan/phase output, real number: real_phase <= real(conv_integer(Aout))*2.0*math_pi/real(2**Z_WIDTH)
        );
end component;


constant WIDTH          :integer := 16;
constant XY_WIDTH       :integer := 20;
constant PIPELENGTH     :integer := 15;
constant Z_WIDTH        :integer := 20;
constant OUT_WIDTH      :integer := 12;

function SIN_GEN(n:natural) return signed is
variable result	: signed(WIDTH-1 downto 0);
begin
	case n is
		when 0	=> result := conv_signed(integer(sin(0.1*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 1	=> result := conv_signed(integer(sin(0.3*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 2	=> result := conv_signed(integer(sin(0.5*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 3	=> result := conv_signed(integer(sin(0.7*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 4	=> result := conv_signed(integer(sin(0.9*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 5	=> result := conv_signed(integer(sin(1.1*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 6	=> result := conv_signed(integer(sin(1.3*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 7	=> result := conv_signed(integer(sin(1.7*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 8	=> result := conv_signed(integer(sin(1.9*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 9	=> result := conv_signed(integer(sin(0.0*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when others => result := conv_signed(integer(sin(0.0*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
	end case;
	return result;
end function;

function COS_GEN(n:natural) return signed is
variable result	: signed(WIDTH-1 downto 0);
begin
	case n is
		when 0	=> result := conv_signed(integer(cos(0.1*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 1	=> result := conv_signed(integer(cos(0.3*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 2	=> result := conv_signed(integer(cos(0.5*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 3	=> result := conv_signed(integer(cos(0.7*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 4	=> result := conv_signed(integer(cos(0.9*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 5	=> result := conv_signed(integer(cos(1.1*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 6	=> result := conv_signed(integer(cos(1.3*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 7	=> result := conv_signed(integer(cos(1.7*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 8	=> result := conv_signed(integer(cos(1.9*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when 9	=> result := conv_signed(integer(cos(0.0*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
		when others => result := conv_signed(integer(cos(0.0*MATH_PI)* 2.0**(WIDTH-4)),WIDTH);
	end case;
	return result;
end function;

signal clk : std_logic;
signal ena : std_logic := '0';
signal Xin : signed(WIDTH-1 downto 0);
signal Yin : signed(WIDTH-1 downto 0);
signal rdy : std_logic;
signal rdy2 : std_logic;
signal Aout: signed(OUT_WIDTH-1 downto 0);
signal Aout2: signed(OUT_WIDTH-1 downto 0);

signal phase_sig     :real;
signal phase_out     :real;
signal phase_out2    :real;

signal  phase_diff_sum  :real;
signal  phase_diff2_sum :real;

signal  phase_diff      : real;
signal  phase_diff2     : real;

FOR I0:  r2p_corproc USE ENTITY WORK.r2p_corproc(SERIAL);
FOR I1:  r2p_corproc USE ENTITY WORK.r2p_corproc(ITERATIVE);


begin

takt_gen: process
         begin
                clk <= '0';
                wait for 20 ns;
                clk <= '1';
                wait for 20 ns;
    end process takt_gen;
    
ena   <= '0', '1' after 500 ns;


process(clk,ena)
    variable cnt : natural range 0 to 50;
    variable ph_cnt :natural range 0 to 9;
begin
   if ena='0' then
      cnt    := 0;
      ph_cnt    := 0;
      Xin    <= (others=>'0');
      Yin    <= (others=>'0');
           
   elsif clk'event and clk='1' then
   	if cnt = 50 then
      		cnt 	  := 0;
      		if ph_cnt = 9 then
      			ph_cnt	:= 0;
      		else
      			ph_cnt	:= ph_cnt + 1;
      		end if;
      	else
      		cnt 	  := cnt + 1;
      	end if;
      	Xin       <= COS_GEN(ph_cnt);
        Yin       <= SIN_GEN(ph_cnt);                       
   else
   end if;
end process;

I0: r2p_corproc
generic map(
   WIDTH => WIDTH,
   XY_WIDTH => XY_WIDTH,
   PIPELENGTH => PIPELENGTH,
   Z_WIDTH => Z_WIDTH,
   OUT_WIDTH => OUT_WIDTH
   )
port map(
        clk => clk,
        ena => ena,
        Xin => Xin,
        Yin => Yin,
        rdy => rdy,
        Aout => Aout
);

I1: r2p_corproc
generic map(
   WIDTH => WIDTH,
   XY_WIDTH => XY_WIDTH,
   PIPELENGTH => PIPELENGTH,
   Z_WIDTH => Z_WIDTH,
   OUT_WIDTH => OUT_WIDTH
   )
port map(
        clk => clk,
        ena => ena,
        Xin => Xin,
        Yin => Yin,
        rdy => rdy2,
        Aout => Aout2
);


--synthesis off
phase_out     <= real(conv_integer(Aout))*2.0*math_pi/real(2**OUT_WIDTH) when Aout>0 else
                 real(conv_integer(Aout))*2.0*math_pi/real(2**OUT_WIDTH) + 2.0*math_pi;
                 
phase_out2    <= real(conv_integer(Aout2))*2.0*math_pi/real(2**OUT_WIDTH) when Aout2>0 else
                 real(conv_integer(Aout2))*2.0*math_pi/real(2**OUT_WIDTH) + 2.0*math_pi;
--synthesis on  


end tb_cordic;