testbench.vhd

本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use work.Signal_Model_pkg.all;

ENTITY testbench IS
END testbench;

ARCHITECTURE tb_cordic OF testbench IS

component r2p_corproc is
        generic(
                WIDTH           : natural := 20;           -- Width of input
                XY_WIDTH        : natural := 24;           -- Width of X and Y-vector, must be greater than WIDTH!
                Z_WIDTH         : natural := 24;           -- Width of Z-vector, must be greater than OUT_WIDTH
                PIPELENGTH      : natural := 15;           -- number of cascades, affects precision
                OUT_WIDTH       : natural := 12            -- output width, must be smaller than Z_WIDTH
                         
        );
        port(
                clk     : in std_logic;
                ena     : in std_logic;
                Xin     : in signed(WIDTH-1 downto 0);
                Yin     : in signed(WIDTH-1 downto 0);
                
                rdy     : out std_logic;                     -- changed by Yue 18/07/2007
                Aout    : out signed(Z_WIDTH-1 downto 0)
        );
end component r2p_corproc;


constant WIDTH          :integer := 16;
constant XY_WIDTH       :integer := 20;
constant PIPELENGTH     :integer := 15;
constant Z_WIDTH        :integer := 20;
constant OUT_WIDTH      :integer := 12;

constant WIDTH2         :integer := 16;
constant XY_WIDTH2      :integer := 20;
constant PIPELENGTH2    :integer := 15;
constant Z_WIDTH2       :integer := 20;
constant OUT_WIDTH2     :integer := 12;

signal clk : std_logic;
signal ena : std_logic := '0';
signal Xin : signed(WIDTH-1 downto 0);
signal Yin : signed(WIDTH-1 downto 0);
signal rdy : std_logic;
signal Aout: signed(OUT_WIDTH-1 downto 0);

signal Xin2  : signed(WIDTH2-1 downto 0);
signal Yin2  : signed(WIDTH2-1 downto 0);
signal rdy2  : std_logic;
signal Aout2 : signed(OUT_WIDTH2-1 downto 0);

signal phase_sig     :real;
signal phase_out     :real;
signal phase_out2    :real;

signal  phase_diff_sum  :real;
signal  phase_diff2_sum :real;

signal  phase_diff      : real;
signal  phase_diff2     : real;

FOR I0:  r2p_corproc USE ENTITY WORK.r2p_corproc(SERIAL);
FOR I1:  r2p_corproc USE ENTITY WORK.r2p_corproc(ITERATIVE);


begin
process(clk,ena)
    variable phase_var          :real;
begin
   if ena='0' then     
      phase_var         := 0.0;
      phase_sig  <= 0.0;
      
      Xin    <= (others=>'0');
      Yin    <= (others=>'0');
      
      Xin2    <= (others=>'0');
      Yin2    <= (others=>'0'); 
           
   elsif clk'event and clk='0' then      
      Phase_gen(phase           => phase_var);
      phase_sig <= phase_var;  
      Xin       <= conv_signed(integer(cos(phase_var)* 2.0**(WIDTH-4)),WIDTH);
      Yin       <= conv_signed(integer(sin(phase_var)* 2.0**(WIDTH-4)),WIDTH);
      Xin2      <= conv_signed(integer(cos(phase_var)* 2.0**(WIDTH2-4)),WIDTH2);
      Yin2      <= conv_signed(integer(sin(phase_var)* 2.0**(WIDTH2-4)),WIDTH2);
                                
   else
   end if;
end process;

I0: r2p_corproc
generic map(
   WIDTH => WIDTH,
   XY_WIDTH => XY_WIDTH,
   PIPELENGTH => PIPELENGTH,
   Z_WIDTH => Z_WIDTH,
   OUT_WIDTH => OUT_WIDTH
   )
port map(
        clk => clk,
        ena => ena,
        Xin => Xin,
        Yin => Yin,
        rdy => rdy,
        Aout => Aout
);

I1: r2p_corproc
generic map(
   WIDTH => WIDTH2,
   XY_WIDTH => XY_WIDTH2,
   PIPELENGTH => PIPELENGTH2,
   Z_WIDTH => Z_WIDTH2,
   OUT_WIDTH => OUT_WIDTH2
   )
port map(
        clk => clk,
        ena => ena,
        Xin => Xin2,
        Yin => Yin2,
        rdy => rdy2,
        Aout => Aout2
);

takt_gen: process
         begin
                clk <= '0';
                wait for 20 ns;
                clk <= '1';
                wait for 20 ns;
    end process takt_gen;
    
ena   <= '0', '1' after 500 ns;
                
phase_out     <= real(conv_integer(Aout))*2.0*math_pi/real(2**OUT_WIDTH) when Aout>0 else
                 real(conv_integer(Aout))*2.0*math_pi/real(2**OUT_WIDTH) + 2.0*math_pi;
                 
phase_out2    <= real(conv_integer(Aout2))*2.0*math_pi/real(2**OUT_WIDTH2) when Aout2>0 else
                 real(conv_integer(Aout2))*2.0*math_pi/real(2**OUT_WIDTH2) + 2.0*math_pi;
                    
 --Genauigkeitsberechnung begin
 precision:process(phase_out, phase_out2, rdy, rdy2)
 begin
  if rdy = '1' then
    if phase_out'event then
         phase_diff      <= abs(phase_out-phase_sig);
         phase_diff_sum  <= phase_diff + phase_diff_sum;
    end if;
  else
         phase_diff     <= 0.0;
         phase_diff_sum <= 0.0;
  end if;
  
  if rdy2 = '1' then
    if phase_out2'event then
         phase_diff2      <= abs(phase_out2-phase_sig);
         phase_diff2_sum  <= phase_diff2 + phase_diff2_sum;
    end if;
  else
         phase_diff2     <= 0.0;
         phase_diff2_sum <= 0.0;
  end if;
 end process precision;
   --Genauigkeitsberechnung end         


end tb_cordic;