r2p_cordic.vhd

本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法

--
--      VHDL implementation of cordic algorithm
--
-- File: cordic.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
-- rev. 1.1 changed CordicPipe component declaration, Xilinx WebPack issue
-- rev. 1.2 Revised entire core. Made is simpler and easier to understand.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;

entity r2p_cordic is 
        generic(
                PIPELINE      : integer := 15;
                WIDTH         : integer := 16;
                XY_WIDTH      : integer := 24;
                Z_WIDTH       : integer := 20
        );
        port(
                clk : in std_logic;
                ena : in std_logic;

                Xi : in signed(WIDTH-1 downto 0);
                Yi : in signed(WIDTH-1 downto 0);
                Zi : in signed(Z_WIDTH-1 downto 0) := (others => '0');
                
                Xo : out signed(XY_WIDTH -1 downto 0);  --Uncorrected Radius
                Zo : out signed(Z_WIDTH-1 downto 0)     --Unswapped Phase
        );
end r2p_cordic;


architecture dataflow of r2p_cordic is

        --
        --      TYPE defenitions
        --
        type XYVector is array(PIPELINE downto 0) of signed(XY_WIDTH -1 downto 0);
        type ZVector is array(PIPELINE downto 0) of signed(Z_WIDTH-1 downto 0);
	    type AtanVector is array(PIPELINE-1 downto 0) of signed(Z_WIDTH-1 downto 0);

        --
        --      COMPONENT declarations
        --
        component r2p_CordicPipe is 
        generic(
                WIDTH           : natural := XY_WIDTH;
                PIPEID          : natural := 1;
                Z_WIDTH         : integer := Z_WIDTH
        );
        port(
                clk             : in std_logic;
                ena             : in std_logic;

                Xi              : in signed(XY_WIDTH -1 downto 0); 
                Yi              : in signed(XY_WIDTH -1 downto 0);
                Zi              : in signed(Z_WIDTH-1 downto 0);
                Xo              : out signed(XY_WIDTH -1 downto 0);
                Yo              : out signed(XY_WIDTH -1 downto 0);
                Zo              : out signed(Z_WIDTH-1 downto 0)
        );
        end component r2p_CordicPipe;

        --
        --      SIGNALS
        --
        signal X, Y     : XYVector;
        signal Z        : ZVector;

begin
        -- fill first nodes, extension LSBS to reach better accuracy
        X(0)(XY_WIDTH -1        downto XY_WIDTH -2)       <= (others => '0');  -- BL: 2 additional MSB to avoid any overflow
        X(0)(XY_WIDTH -3        downto XY_WIDTH -WIDTH-2) <= Xi;               -- fill MSBs with input data
        X(0)(XY_WIDTH -WIDTH -3 downto 0)                 <= (others => '0');  -- fill LSBs with '0'

        y(0)(XY_WIDTH -1        downto XY_WIDTH -2)       <= (others => '0');  -- BL: 2 additional MSB to avoid any overflow
        Y(0)(XY_WIDTH -3        downto XY_WIDTH -WIDTH-2) <= Yi;               -- fill MSBs with input data
        Y(0)(XY_WIDTH -WIDTH -3 downto 0)                 <= (others => '0');  -- fill LSBs with '0'

        Z(0) <= Zi;

        --
        -- generate pipeline
        --
        gen_pipe:
        for n in 1 to PIPELINE generate
          Pipe: r2p_CordicPipe 
          generic map
          (
            WIDTH   => XY_WIDTH, 
            PIPEID  => n -1, 
            Z_WIDTH => Z_WIDTH
          )
          port map 
          ( 
            clk, 
            ena, 
            X(n-1), 
            Y(n-1), 
            Z(n-1), 
            X(n), 
            Y(n), 
            Z(n)
          );
        end generate gen_pipe;

        --
        -- assign outputs
        --
        Xo <= X(PIPELINE);
        Zo <= Z(PIPELINE);
end dataflow;