r2p_core.vhd

本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法

--
-- file: r2p_CordicPipe.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
-- rev. 1.1 March 19th, 2001. Richard Herveille. Changed function Delta, it is compatible with Xilinx WebPack software now
-- rev. 1.2 May   18th, 2001. Richard Herveille. Added documentation to function ATAN (by popular request).
-- rev. 1.3 June   4th, 2001. Richard Herveille. Revised design (made it simpler and easier to understand). 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;

entity r2p_core is 
        generic(
                WIDTH   : natural := 16;
                Z_WIDTH    : integer := 20;                     -- changed by Yue 16/07/2007
                PIPELENGTH  : integer := 15
        );
        port(
                clk             : in std_logic;
                ena             : in std_logic;

                Xi              : in  signed(WIDTH -1 downto 0); 
                Yi              : in  signed(WIDTH -1 downto 0);
                Zi              : in  signed(Z_WIDTH-1 downto 0); -- changed by Yue 16/07/2007
                PipeID          : in  natural;
                Xo              : out signed(WIDTH -1 downto 0);
                Yo              : out signed(WIDTH -1 downto 0);
                Zo              : out signed(Z_WIDTH-1 downto 0) -- changed by Yue 16/07/2007
        );
end entity r2p_core;

architecture dataflow of r2p_core is

        -- shiftn module is not in use any more, implemented as function under
        --Component shiftn IS
        --   GENERIC( 
        --      WIDTH : integer := 16;
        --      PIPELENGTH :integer := 15  -- here is not generic for this module! must modify the module
        --   );
        --   PORT( 
        --      ibus  : IN   signed(WIDTH-1 DOWNTO 0);
        --      obus  : OUT  signed(WIDTH-1 DOWNTO 0);
        --      n     : IN   natural
        --   );
        --END Component;
        


        --
        -- functions
        --

        -- Function CATAN (constante arc-tangent).
        -- This is a lookup table containing pre-calculated arc-tangents.
        -- 'n' is the number of the pipe, returned is a 20bit arc-tangent value.
        -- The numbers are calculated as follows: Z(n) = atan(1/2^n)
        -- examples:
        -- 20bit values => 2^20 = 2pi(rad)
        --                 1(rad) = 2^20/2pi = 166886.053....
        -- n:1, atan(1/2) = 0.4636...(rad)
        --      0.4636... * 166886.053... = 77376.32(dec) = 12E40(hex)
        -- n:2, atan(1/4) = 0.2449...(rad)
        --      0.2449... * 166886.053... = 40883.52(dec) = 9FB3(hex)
        -- n:3, atan(1/8) = 0.1243...(rad)
        --      0.1243... * 166886.053... = 20753.11(dec) = 5111(hex)
        --
        --function CATAN(n :natural) return signed is
        --variable result       :integer;
        --begin
        --      case n is
        --              when 0 => result := integer(arctan(1.0/(2.0**0)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 1 => result := integer(arctan(1.0/(2.0**1)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 2 => result := integer(arctan(1.0/(2.0**2)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 3 => result := integer(arctan(1.0/(2.0**3)) * 2.0**Z_WIDTH/(2.0*math_pi));
         --             when 4 => result := integer(arctan(1.0/(2.0**4)) * 2.0**Z_WIDTH/(2.0*math_pi));
         --             when 5 => result := integer(arctan(1.0/(2.0**5)) * 2.0**Z_WIDTH/(2.0*math_pi));
         --             when 6 => result := integer(arctan(1.0/(2.0**6)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 7 => result := integer(arctan(1.0/(2.0**7)) * 2.0**Z_WIDTH/(2.0*math_pi));
         --             when 8 => result := integer(arctan(1.0/(2.0**8)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 9 => result := integer(arctan(1.0/(2.0**9)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 10 => result := integer(arctan(1.0/(2.0**10)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 11 => result := integer(arctan(1.0/(2.0**11)) * 2.0**Z_WIDTH/(2.0*math_pi));
         --             when 12 => result := integer(arctan(1.0/(2.0**12)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 13 => result := integer(arctan(1.0/(2.0**13)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 14 => result := integer(arctan(1.0/(2.0**14)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 15 => result := integer(arctan(1.0/(2.0**15)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 16 => result := integer(arctan(1.0/(2.0**16)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when 17 => result := integer(arctan(1.0/(2.0**17)) * 2.0**Z_WIDTH/(2.0*math_pi));
        --              when others => result := 0;
        --      end case;
        --      return conv_signed(result, Z_WIDTH);
        --end CATAN;
        
        --for "SHR" library-function in std_logic_arith
        constant cnt_len   :integer := integer(CEIL(LOG2(real(PIPELENGTH))));
        
        --new generic CATAN-lookup-table
        function CATAN(n :natural) return signed is
        TYPE Atan_vec is array(PIPELENGTH-1 downto 0) of signed(Z_WIDTH-1 downto 0);
        variable Atan  : Atan_vec;
        begin
            for i in Atan'RANGE loop
                 Atan(i) := conv_signed(integer(arctan(1.0/(2.0**i)) * 2.0**Z_WIDTH/(2.0*math_pi)), Z_WIDTH);
            end loop;
            return Atan(n);
        end CATAN;
        
        --parametrisizable shifter
        --function Shift_right(n :natural; ibus:signed) return signed is
        --type     shifed_vec is array (PIPELENGTH-1 downto 0) of signed(WIDTH-1 downto 0);
        --variable shifted : shifed_vec;
        --begin
        --     for i in 0 to PIPELENGTH-1 loop
        --         shifted(i) := SHR(ibus, conv_unsigned(i, cnt_len));
        --     end loop;
        --     return shifted(n);
        --end Shift_right;
        
        --new parametrisizable shifter
        function Shift_right(n :natural; ibus:signed) return signed is
        variable shifted : signed(WIDTH-1 downto 0);
        begin
             shifted := SHR(ibus, conv_unsigned(n, cnt_len));
             return shifted;
        end Shift_right;
    
        --simple ALU
        function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is
        begin
                if (add_sub = '1') then
                        return dataa + datab;
                else
                        return dataa - datab;
                end if;
        end;

        --
        --      ARCHITECTURE BODY
        --
        signal dX, Xresult      : signed(WIDTH -1 downto 0);
        signal dY, Yresult      : signed(WIDTH -1 downto 0);
        signal atan, Zresult    : signed(Z_WIDTH-1 downto 0);     -- changed by Yue 16/07/2007

        signal Yneg, Ypos       : std_logic;

begin

        --Shift1 : shiftn
        --generic map(WIDTH => WIDTH, PIPELENGTH => PIPELENGTH)
        --port map(ibus => Xi, obus => dX, n => PipeID);


        --Shift2 : shiftn
        --generic map(WIDTH => WIDTH, PIPELENGTH => PIPELENGTH)
        --port map(ibus => Yi, obus => dY, n => PipeID);
        
        dX <= Shift_right(PipeID, Xi);
        dY <= Shift_right(PipeID, Yi);

        --dX <= Delta(Xi, PipeID);                                --function call only for simulation!!!!
        --dY <= Delta(Yi, PipeID);                                --function call only for simulation!!!!
        --atan <= conv_signed(CATAN(PipeID), Z_WIDTH);            --function call only for simulation!!!!
        atan <= CATAN(PipeID);
        
        -- generate adder structures
        Yneg <= Yi(WIDTH -1);
        Ypos <= not Yi(WIDTH -1);

        -- xadd
        Xresult <= AddSub(Xi, dY, YPos);

        -- yadd 
        Yresult <= AddSub(Yi, dX, Yneg);

        -- zadd
       
        Zresult <= AddSub(Zi, atan, Ypos);

        gen_regs: process(clk)
        begin
                if(clk'event and clk='1') then
                        if (ena = '1') then
                                Xo <= Xresult;
                                Yo <= Yresult;
                                Zo <= Zresult;
                        end if;
                end if;
        end process;

end architecture dataflow;