r2p_cordicpipe.vhd

本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法

--
-- file: r2p_CordicPipe.vhd
-- author: Richard Herveille
-- rev. 1.0 initial release
-- rev. 1.1 March 19th, 2001. Richard Herveille. Changed function Delta, it is compatible with Xilinx WebPack software now
-- rev. 1.2 May   18th, 2001. Richard Herveille. Added documentation to function ATAN (by popular request).
-- rev. 1.3 June   4th, 2001. Richard Herveille. Revised design (made it simpler and easier to understand). 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.math_real.all;

entity r2p_CordicPipe is 
        generic(
                WIDTH   : natural := 16;
                PIPEID  : natural := 0;
                Z_WIDTH    : integer := 20                     -- changed by Yue 16/07/2007
        );
        port(
                clk             : in std_logic;
                ena             : in std_logic;

                Xi              : in  signed(WIDTH -1 downto 0); 
                Yi              : in  signed(WIDTH -1 downto 0);
                Zi              : in  signed(Z_WIDTH-1 downto 0); -- changed by Yue 16/07/2007
                Xo              : out signed(WIDTH -1 downto 0);
                Yo              : out signed(WIDTH -1 downto 0);
                Zo              : out signed(Z_WIDTH-1 downto 0) -- changed by Yue 16/07/2007
        );
end entity r2p_CordicPipe;

architecture dataflow of r2p_CordicPipe is


        -- function Delta is actually an arithmatic shift right
        -- This strange construction is needed for compatibility with Xilinx WebPack
        function Delta(Arg : signed; Cnt : natural) return signed is
                variable tmp : signed(Arg'range);
                constant lo : integer := Arg'high -cnt +1;
        begin
                for n in Arg'high downto lo loop
                        tmp(n) := Arg(Arg'high);
                end loop;
                for n in Arg'high -cnt downto 0 loop
                        tmp(n) := Arg(n +cnt);
                end loop;
                return tmp;
        end function Delta;

        function AddSub(dataa, datab : in signed; add_sub : in std_logic) return signed is
        begin
                if (add_sub = '1') then
                        return dataa + datab;
                else
                        return dataa - datab;
                end if;
        end;

        --
        --      ARCHITECTURE BODY
        --
        constant Atan :signed(Z_WIDTH-1 downto 0) := conv_signed(integer(arctan(1.0/(2.0**PIPEID)) * 2.0**Z_WIDTH/(2.0*math_pi)), Z_WIDTH);
        
        signal dX, Xresult      : signed(WIDTH -1 downto 0);
        signal dY, Yresult      : signed(WIDTH -1 downto 0);
        signal Zresult    	     : signed(Z_WIDTH-1 downto 0);     -- changed by Yue 16/07/2007

        signal Yneg, Ypos       : std_logic;

begin

        dX <= Delta(Xi, PIPEID);
        dY <= Delta(Yi, PIPEID);
                                                       -- Angle can not be negative, catan never returns a negative value, so conv_signed can be used

        -- generate adder structures
        Yneg <= Yi(WIDTH -1);
        Ypos <= not Yi(WIDTH -1);

        -- xadd
        Xresult <= AddSub(Xi, dY, YPos);

        -- yadd 
        Yresult <= AddSub(Yi, dX, Yneg);

        -- zadd
        Zresult <= AddSub(Zi, Atan, Ypos);  --Changed by Yue 18/07/2007

        gen_regs: process(clk)
        begin
                if(clk'event and clk='1') then
                        if (ena = '1') then
                                Xo <= Xresult;
                                Yo <= Yresult;
                                Zo <= Zresult;
                        end if;
                end if;
        end process;

end architecture dataflow;