r2p_corproc.vhd

本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity r2p_corproc is
generic
(
  RADIUS_CORRECTION    : boolean := true;        -- Corrects the radius by multiplication with 0.60650 if true, !needs additional ressources!
  Input_width          : natural := 8;           -- Width of input vectors Xin,Yin
  Phase_width          : natural := 7;           -- Width of Z-vector defines phase resolution
  Pipe_size            : natural := 7            -- Number of iterations affects precision
);
port
(
  clk     : in std_logic;
  ena     : in std_logic;                         -- global synchronous enable with '1' as actived
  Xin     : in signed(Input_width-1 downto 0);    -- value of denominator
  Yin     : in signed(Input_width-1 downto 0);    -- value of numerator
  rdy     : out std_logic;                        -- ready Signal, '1' indicates data available on output 
  Phase   : out signed(Phase_width-1 downto 0);   -- Arctan/phase output, real number: real_phase <= real(conv_integer(Phase))*2.0*math_pi/real(2**Phase_width)
  Radius  : out unsigned(Input_Width+7 downto 0)  -- Fix(Input_Width+8.6), corrected if RADIUS_CORRECTION is set to true
);
end entity r2p_corproc;

-------------------------------------------------------------------------------
----------- Architechture1: Serial implementation of Cordic--------------------
-------------------------------------------------------------------------------
architecture SERIAL of r2p_corproc is
  --constants--
    constant XY_WIDTH  : integer := Input_Width+8;  --+8 is needed to reach precision for small Xin and Yin due to shift operations in cordic pipe

  --components--
    component r2p_pre is
    generic
    (
      WIDTH   : integer := 16             
    );
    port
    (
      clk     : in std_logic;
      ena     : in std_logic;
      Xi      : in signed(WIDTH-1 downto 0);     
      Yi      : in signed(WIDTH-1 downto 0);          
      Xo      : out unsigned(WIDTH-2 downto 0);   
      Yo      : out unsigned(WIDTH-2 downto 0);
      Q       : out std_logic_vector(2 downto 0)
    );
    end component;
    
    component r2p_cordic is 
    generic
    (
      WIDTH         : integer := 16;
      XY_WIDTH      : integer := 20;
      PIPELINE      : integer := 15;
      Z_WIDTH       : integer := 20     
    );
    port
    (
      clk : in std_logic;
      ena : in std_logic;
      Xi  : in signed(WIDTH-1 downto 0);
      Yi  : in signed(WIDTH-1 downto 0);
      Zi  : in signed(Z_WIDTH-1 downto 0) := (others => '0');
      Xo  : out signed(XY_WIDTH -1 downto 0);  --Uncorrected Radius
      Zo  : out signed(Z_WIDTH-1 downto 0)     --Unswapped Phase                       
    );
    end component;

    component r2p_post is
    generic
    (
	    RADIUS_CORRECTION    : boolean := true;
		WIDTH 	             : natural := 16;
		Z_WIDTH              : integer := 20;
		XY_WIDTH             : integer := 18                     
    );
    port
    (
		clk	 : in std_logic;
		ena	 : in std_logic;
		Ai	 : in signed(Z_WIDTH-1 downto 0);     
		Ri	 : in unsigned(XY_WIDTH -1 downto 0);
		Q	 : in std_logic_vector(2 downto 0);
		Ro	 : out unsigned(XY_WIDTH -1 downto 0);
		Ao 	 : out signed(Z_WIDTH-1 downto 0)
    );
    end component r2p_post;

  --signals--
    signal Xpre, Ypre : unsigned(Input_width-1 downto 0);
    signal Acor       : signed(Phase_width-1 downto 0);
    signal Rcor       : signed(XY_WIDTH -1 downto 0);  --Uncorrected Radius
    signal Q, dQ      : std_logic_vector(2 downto 0);

----------------------------------------------------------------------------------------------
begin-----------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------

  --Cordic preprocessing
    --swap x<->y if y>0
    --store sign of x,y
	u1: r2p_pre 
    generic map
    (
      WIDTH => Input_width
    )
    port map
    (
      clk => clk, 
      ena => ena, 
      Xi  => Xin, 
      Yi  => Yin, 
      Xo  => Xpre(Input_width-2 downto 0), 
      Yo  => Ypre(Input_width-2 downto 0), 
      Q   => Q
    );       
    Xpre(Input_width-1) <= '0';   -- the MSB indicates positive output 
    Ypre(Input_width-1) <= '0';

  --Cordic pipeline in serial configuration
    u2: r2p_cordic      
    generic map
    (
      PIPELINE => Pipe_size, 
      WIDTH    => Input_width, 
      XY_WIDTH => XY_WIDTH, 
      Z_WIDTH  => Phase_width
    )
    port map
    (
      clk => clk, 
      ena => ena, 
      Xi  => signed(Xpre), 
      Yi  => signed(Ypre), 
      Zi  => (others=>'0'),
      Xo  => Rcor,   
      Zo  => Acor
    );   

  --delay of x,y sign information from cordic preprocessing
    delay: block
      type delay_type is array(Pipe_size -1 downto 0) of std_logic_vector(2 downto 0);
      signal delay_pipe :delay_type;
    begin
      process(clk, Q)
      begin
        if (clk'event and clk = '1') then
          if (ena = '1') then
            delay_pipe(0) <= Q;
            for n in 1 to Pipe_size -1 loop
              delay_pipe(n) <= delay_pipe(n -1);
            end loop;
          end if;
        end if;
      end process;
      dQ <= delay_pipe(Pipe_size -1);
    end block delay;

  --Cordic postprocessing
    --Add sign information
    --Reverse swap of x,y
    u3: r2p_post
    generic map
    (
      RADIUS_CORRECTION => RADIUS_CORRECTION,
      WIDTH             => Input_width, 
      Z_WIDTH           => Phase_width,
      XY_WIDTH          => XY_WIDTH
    ) 
    port map
    (
      clk => clk,  
      ena => ena, 
      Ai  => Acor,
      Ri  => unsigned(Rcor), 
      Q   => dQ,
      Ro  => Radius, 
      Ao  => Phase
    );
  
  --Generates ready signal when phase is valid                                      
    ready: block
      constant cordic_delay  :natural := Pipe_size+7; 
      signal rdy_pipe :std_logic_vector(cordic_delay-1 downto 0);
    begin
      process(clk)
      begin
        if (clk'event and clk = '1') then
          if (ena = '1') then
            rdy_pipe(0) <= '1';
            for n in 1 to cordic_delay-1 loop
              rdy_pipe(n) <= rdy_pipe(n-1);
            end loop;
          else
            rdy_pipe <= (others=>'0'); 
          end if;
        else
        end if;
      end process;
      rdy <= rdy_pipe(rdy_pipe'high);
    end block ready;

end architecture SERIAL;