bread_s.v

一个RAM的测试仿真程序

 `timescale 1ps / 1ps
module Bread_s
	(
		clk,
		rst_n,
		Bread_CE,
		cmdack,
		addr,
		dataout,
		cmd,
		Bfinish_R,
		dm,
		toLED
	);
  
  	input         clk;
	input         rst_n;
	input         Bread_CE;//高电平此模块有效
	input         cmdack;
	output [2:0]  cmd;
	output [22:0] addr;
	input [15:0]  dataout; 
	output        Bfinish_R;
	output [1:0]  dm;
	output [3:0]  toLED;
	
	
	parameter s0 = 0, s1 = 1, s2 = 2, IDLE = 3;
   
	reg [2:0]  state;
	reg [2:0]  next_state;
	
	reg [22:0] addr;
	reg [15:0] datain;
	reg [2:0]  cmd;
	reg[1:0]   dm;
	reg        Bfinish_R;
	wire [3:0]  toLED;
	
	assign toLED[3:0] = dataout[3:0]; //其起始数据是15。
   //---------时序进程-----------------------------------------
	always @ (posedge clk)
		if (!rst_n)
			begin
			state <= IDLE;
			end
		else
			state <= next_state;
	//---------状态转换进程------------------------------------
	always @ (state or cmdack or Bread_CE)
		case (state)
	//-------以下是写sdram程序---------------------------------
			s0 :
			
			begin
			    addr[22:0]<= 23'd16 ;  //起始地址是15。
				cmd <= 3'b001;  //带自动预充电的写.
				dm <=4'b00;
				Bfinish_R <= 0;
                if (cmdack == 1)  // Wait for the controller to ack the command  
                	next_state <= s1;  
              	else 
                 	next_state <= s0;  
			end
			
			s1 :
			begin
			    addr[22:0]<= 23'd0 ;  
			    cmd <= 3'b000;  //带自动预充电的写.
				dm <=4'b00;
				Bfinish_R <= 1;
				next_state <= s2; 
            end

			s2:
			begin
			    addr[22:0]<=23'bz;
				cmd <= 3'bz;//nop
			    dm <=4'bz;  //没有屏蔽位
				Bfinish_R <= 1;
			   	next_state <= IDLE;
            end

			IDLE:
			begin
		    	if (Bread_CE == 1)
					begin
			    	next_state <= s0;
					Bfinish_R <= 0;
					cmd <= 3'bz;
					addr[22:0]<=23'bz;
					dm <=4'bz;
					end
				else
					begin
		   				addr[22:0]<=23'bz;
						cmd <= 3'bz;//nop
						dm <=4'bz;
						next_state <= IDLE;
						Bfinish_R <= 0;
					end
			end
			 	
			default: 
				begin 
				addr[22:0]<=23'bz;
				cmd <= 3'bz;//nop
				dm <=4'bz;
				next_state <= IDLE;
				Bfinish_R <= 0;
				end
		endcase

endmodule