main_s.v

来自「一个RAM的测试仿真程序」· Verilog 代码 · 共 113 行

`timescale 1ps / 1ps
module main_s
(
clk,
rst_n,
finish_F,
Bfinish_W,
Bfinish_R,
config_CE,
Bwrite_CE,
Bread_CE
);

input         clk;
input         rst_n;
input         finish_F;
input         Bfinish_W;
input         Bfinish_R;
output        config_CE;//高电平此模块有效
output        Bwrite_CE;
output        Bread_CE;



parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5, IDLE = 6;

reg [2:0]  state;
reg [2:0]  next_state;
reg        config_CE;
reg        Bwrite_CE;
reg        Bread_CE;
//---------时序进程-----------------------------------------
always @ (posedge clk)
if (!rst_n)
begin
state <= s0;
end

else
state <= next_state;
//---------状态转换进程------------------------------------
always @ (state or finish_F or Bfinish_W or Bfinish_R)
case (state)

s0 :
begin
config_CE <= 1;//保证2个时钟周期都是1。
Bwrite_CE <= 0;
Bread_CE <= 0;
next_state <= s1;  
end
s1 :
begin
config_CE <= 1;
Bwrite_CE <= 0;
Bread_CE <= 0;
if (finish_F == 1)  // Wait for the controller to ack the command  
next_state <= s2;
else 
next_state <= s1;
end
s2 :
begin
config_CE <= 0;
Bwrite_CE <= 1;
Bread_CE <= 0;
next_state <= s3;  
end
s3 :
begin
config_CE <= 0;
Bwrite_CE <= 1;
Bread_CE <= 0;
if (Bfinish_W == 1)  // Wait for the controller to ack the command  
next_state <= s4;
else 
next_state <= s3;
end
s4 :
begin
config_CE <= 0;
Bwrite_CE <= 0;
Bread_CE <= 1;
next_state <= s5;  
end
s5 :
begin
config_CE <= 0;
Bwrite_CE <= 0;
Bread_CE <= 1;
if (Bfinish_R == 1)  // Wait for the controller to ack the command  
next_state <= IDLE;
else 
next_state <= s5;
end
IDLE:
begin
config_CE <= 0;
Bwrite_CE <= 0;
Bread_CE <=  0;
next_state <= IDLE;
end

default: 
begin 
config_CE <= 0;
Bwrite_CE <= 0;
Bread_CE <= 0;
next_state <= s0;
end
endcase
endmodule