_primary.vhd

来自「一个RAM的测试仿真程序」· VHDL 代码 · 共 28 行

library verilog;
use verilog.vl_types.all;
entity config_s is
    generic(
        s0              : integer := 0;
        s1              : integer := 1;
        s2              : integer := 2;
        s3              : integer := 3;
        s4              : integer := 4;
        s5              : integer := 5;
        s6              : integer := 6;
        s7              : integer := 7;
        s8              : integer := 8;
        s9              : integer := 9;
        IDLE            : integer := 10
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        config_CE       : in     vl_logic;
        cmdack          : in     vl_logic;
        addr            : out    vl_logic_vector(22 downto 0);
        datain          : out    vl_logic_vector(15 downto 0);
        cmd             : out    vl_logic_vector(2 downto 0);
        finish_F        : out    vl_logic
    );
end config_s;