_primary.vhd

来自「一个RAM的测试仿真程序」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity main_s is
    generic(
        s0              : integer := 0;
        s1              : integer := 1;
        s2              : integer := 2;
        s3              : integer := 3;
        s4              : integer := 4;
        s5              : integer := 5;
        IDLE            : integer := 6
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        finish_F        : in     vl_logic;
        Bfinish_W       : in     vl_logic;
        Bfinish_R       : in     vl_logic;
        config_CE       : out    vl_logic;
        Bwrite_CE       : out    vl_logic;
        Bread_CE        : out    vl_logic
    );
end main_s;