main_top.v

一个RAM的测试仿真程序

`include        "main_s.v"
`include        "Bwrite_s.v"
`include        "Bread_s.v"
`include        "config_s.v"
module main_top(
	clk,
	rst_n,
	cmdack,
	dataout,
	cmd,
	addr,
	datain,
	dm,
	toLED
);
//---------sdram控制器输入信号----------------------
//

input	clk;
input	rst_n;
input   cmdack;
input  [15:0] dataout;
output [2:0]  cmd;
output [22:0] addr;
output [15:0] datain;
output [1:0]  dm;
output [3:0]  toLED;




wire finish_F;
wire Bfinish_W;
wire Bfinish_R;
wire config_CE;
wire Bwrite_CE;
wire Bread_CE;

main_s main_s1 (
                 .clk(clk),
                 .rst_n(rst_n),
                 .finish_F(finish_F),
                 .Bfinish_W(Bfinish_W),
                 .Bfinish_R(Bfinish_R),
                 .config_CE(config_CE),
                 .Bwrite_CE(Bwrite_CE),
                 .Bread_CE(Bread_CE)
               );  
config_s config_s1
                (
                 .clk(clk),
                 .rst_n(rst_n),
                 .config_CE(config_CE),
				 .cmdack(cmdack),
				 .addr(addr),
 				 .datain(datain) ,
				 .cmd(cmd),
                 .finish_F(finish_F)         
     );
Bwrite_s Bwrite_s1
                (
                 .clk(clk),
                 .rst_n(rst_n),
                 .Bwrite_CE(Bwrite_CE),
				 .cmdack(cmdack),
				 .addr(addr),
 				 .datain(datain) ,
				 .cmd(cmd),
                 .Bfinish_W(Bfinish_W),
                 .dm(dm)       
     );
Bread_s Bread_s1
                (
                 .clk(clk),
                 .rst_n(rst_n),
                 .Bread_CE(Bread_CE),
				 .cmdack(cmdack),
				 .addr(addr),
 				 .dataout(dataout) ,
				 .cmd(cmd),
                 .Bfinish_R(Bfinish_R),
                 .dm(dm),
                 .toLED(toLED)       
     );

endmodule