prev_cmp_ram.tan.qmsg

来自「用VerilogHDL写的ram程序」· QMSG 代码 · 共 11 行 · 第 1/2 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[4\] temp_data\[4\] 8.584 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[4\]\" through register \"temp_data\[4\]\" is 8.584 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.202 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk 1 CLK PIN_R25 32 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R25; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.774 ns) + CELL(0.560 ns) 3.202 ns temp_data\[4\] 2 REG LC_X33_Y10_N1 1 " "Info: 2: + IC(1.774 ns) + CELL(0.560 ns) = 3.202 ns; Loc. = LC_X33_Y10_N1; Fanout = 1; REG Node = 'temp_data\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk temp_data[4] } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.60 % ) " "Info: Total cell delay = 1.428 ns ( 44.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.774 ns ( 55.40 % ) " "Info: Total interconnect delay = 1.774 ns ( 55.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.202 ns" { clk temp_data[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.202 ns" { clk {} clk~out0 {} temp_data[4] {} } { 0.000ns 0.000ns 1.774ns } { 0.000ns 0.868ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.206 ns + Longest register pin " "Info: + Longest register to pin delay is 5.206 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp_data\[4\] 1 REG LC_X33_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y10_N1; Fanout = 1; REG Node = 'temp_data\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { temp_data[4] } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns q~349 2 COMB LC_X33_Y10_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC_X33_Y10_N1; Fanout = 1; COMB Node = 'q~349'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.291 ns" { temp_data[4] q~349 } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.411 ns) + CELL(2.504 ns) 5.206 ns q\[4\] 3 PIN PIN_AB10 0 " "Info: 3: + IC(2.411 ns) + CELL(2.504 ns) = 5.206 ns; Loc. = PIN_AB10; Fanout = 0; PIN Node = 'q\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.915 ns" { q~349 q[4] } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.795 ns ( 53.69 % ) " "Info: Total cell delay = 2.795 ns ( 53.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.411 ns ( 46.31 % ) " "Info: Total interconnect delay = 2.411 ns ( 46.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.206 ns" { temp_data[4] q~349 q[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.206 ns" { temp_data[4] {} q~349 {} q[4] {} } { 0.000ns 0.000ns 2.411ns } { 0.000ns 0.291ns 2.504ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.202 ns" { clk temp_data[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.202 ns" { clk {} clk~out0 {} temp_data[4] {} } { 0.000ns 0.000ns 1.774ns } { 0.000ns 0.868ns 0.560ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.206 ns" { temp_data[4] q~349 q[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.206 ns" { temp_data[4] {} q~349 {} q[4] {} } { 0.000ns 0.000ns 2.411ns } { 0.000ns 0.291ns 2.504ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "en q\[4\] 11.080 ns Longest " "Info: Longest tpd from source pin \"en\" to destination pin \"q\[4\]\" is 11.080 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns en 1 PIN PIN_V18 32 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_V18; Fanout = 32; PIN Node = 'en'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.937 ns) + CELL(0.087 ns) 6.165 ns q~349 2 COMB LC_X33_Y10_N1 1 " "Info: 2: + IC(4.937 ns) + CELL(0.087 ns) = 6.165 ns; Loc. = LC_X33_Y10_N1; Fanout = 1; COMB Node = 'q~349'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.024 ns" { en q~349 } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.411 ns) + CELL(2.504 ns) 11.080 ns q\[4\] 3 PIN PIN_AB10 0 " "Info: 3: + IC(2.411 ns) + CELL(2.504 ns) = 11.080 ns; Loc. = PIN_AB10; Fanout = 0; PIN Node = 'q\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.915 ns" { q~349 q[4] } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.732 ns ( 33.68 % ) " "Info: Total cell delay = 3.732 ns ( 33.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.348 ns ( 66.32 % ) " "Info: Total interconnect delay = 7.348 ns ( 66.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.080 ns" { en q~349 q[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.080 ns" { en {} en~out0 {} q~349 {} q[4] {} } { 0.000ns 0.000ns 4.937ns 2.411ns } { 0.000ns 1.141ns 0.087ns 2.504ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "temp_data\[16\] data\[16\] clk -1.940 ns register " "Info: th for register \"temp_data\[16\]\" (data pin = \"data\[16\]\", clock pin = \"clk\") is -1.940 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.207 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.207 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk 1 CLK PIN_R25 32 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R25; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.779 ns) + CELL(0.560 ns) 3.207 ns temp_data\[16\] 2 REG LC_X1_Y6_N0 1 " "Info: 2: + IC(1.779 ns) + CELL(0.560 ns) = 3.207 ns; Loc. = LC_X1_Y6_N0; Fanout = 1; REG Node = 'temp_data\[16\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.339 ns" { clk temp_data[16] } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.53 % ) " "Info: Total cell delay = 1.428 ns ( 44.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.779 ns ( 55.47 % ) " "Info: Total interconnect delay = 1.779 ns ( 55.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.207 ns" { clk temp_data[16] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.207 ns" { clk {} clk~out0 {} temp_data[16] {} } { 0.000ns 0.000ns 1.779ns } { 0.000ns 0.868ns 0.560ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 9 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.247 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns data\[16\] 1 PIN PIN_W26 1 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_W26; Fanout = 1; PIN Node = 'data\[16\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { data[16] } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.862 ns) + CELL(0.090 ns) 5.247 ns temp_data\[16\] 2 REG LC_X1_Y6_N0 1 " "Info: 2: + IC(3.862 ns) + CELL(0.090 ns) = 5.247 ns; Loc. = LC_X1_Y6_N0; Fanout = 1; REG Node = 'temp_data\[16\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.952 ns" { data[16] temp_data[16] } "NODE_NAME" } } { "RAM.v" "" { Text "D:/Quartus2/RAM/RAM.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.385 ns ( 26.40 % ) " "Info: Total cell delay = 1.385 ns ( 26.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.862 ns ( 73.60 % ) " "Info: Total interconnect delay = 3.862 ns ( 73.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { data[16] temp_data[16] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.247 ns" { data[16] {} data[16]~out0 {} temp_data[16] {} } { 0.000ns 0.000ns 3.862ns } { 0.000ns 1.295ns 0.090ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.207 ns" { clk temp_data[16] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.207 ns" { clk {} clk~out0 {} temp_data[16] {} } { 0.000ns 0.000ns 1.779ns } { 0.000ns 0.868ns 0.560ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { data[16] temp_data[16] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.247 ns" { data[16] {} data[16]~out0 {} temp_data[16] {} } { 0.000ns 0.000ns 3.862ns } { 0.000ns 1.295ns 0.090ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 12 23:00:36 2008 " "Info: Processing ended: Fri Dec 12 23:00:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}