ram.fit.summary

来自「用VerilogHDL写的ram程序」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Fri Dec 12 23:04:47 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : RAM
Top-level Entity Name : RAM
Family : Stratix
Device : EP1S10F780C6
Timing Models : Final
Total logic elements : 32 / 10,570 ( < 1 % )
Total pins : 69 / 427 ( 16 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )