ram_modelsim.xrf

用VerilogHDL写的ram程序

vendor_name = ModelSim
source_file = 1, D:/Quartus2/RAM/RAM.v
source_file = 1, D:/Quartus2/RAM/RAM.vwf
design_name = RAM
instance = comp, \clk~I , clk, RAM, 1
instance = comp, \data[0]~I , data[0], RAM, 1
instance = comp, \en~I , en, RAM, 1
instance = comp, \temp_data[0] , temp_data[0], RAM, 1
instance = comp, \data[1]~I , data[1], RAM, 1
instance = comp, \temp_data[1] , temp_data[1], RAM, 1
instance = comp, \data[2]~I , data[2], RAM, 1
instance = comp, \temp_data[2] , temp_data[2], RAM, 1
instance = comp, \data[3]~I , data[3], RAM, 1
instance = comp, \temp_data[3] , temp_data[3], RAM, 1
instance = comp, \data[4]~I , data[4], RAM, 1
instance = comp, \temp_data[4] , temp_data[4], RAM, 1
instance = comp, \data[5]~I , data[5], RAM, 1
instance = comp, \temp_data[5] , temp_data[5], RAM, 1
instance = comp, \data[6]~I , data[6], RAM, 1
instance = comp, \temp_data[6] , temp_data[6], RAM, 1
instance = comp, \data[7]~I , data[7], RAM, 1
instance = comp, \temp_data[7] , temp_data[7], RAM, 1
instance = comp, \data[8]~I , data[8], RAM, 1
instance = comp, \temp_data[8] , temp_data[8], RAM, 1
instance = comp, \data[9]~I , data[9], RAM, 1
instance = comp, \temp_data[9] , temp_data[9], RAM, 1
instance = comp, \data[10]~I , data[10], RAM, 1
instance = comp, \temp_data[10] , temp_data[10], RAM, 1
instance = comp, \data[11]~I , data[11], RAM, 1
instance = comp, \temp_data[11] , temp_data[11], RAM, 1
instance = comp, \data[12]~I , data[12], RAM, 1
instance = comp, \temp_data[12] , temp_data[12], RAM, 1
instance = comp, \data[13]~I , data[13], RAM, 1
instance = comp, \temp_data[13] , temp_data[13], RAM, 1
instance = comp, \data[14]~I , data[14], RAM, 1
instance = comp, \temp_data[14] , temp_data[14], RAM, 1
instance = comp, \data[15]~I , data[15], RAM, 1
instance = comp, \temp_data[15] , temp_data[15], RAM, 1
instance = comp, \data[16]~I , data[16], RAM, 1
instance = comp, \temp_data[16] , temp_data[16], RAM, 1
instance = comp, \data[17]~I , data[17], RAM, 1
instance = comp, \temp_data[17] , temp_data[17], RAM, 1
instance = comp, \data[18]~I , data[18], RAM, 1
instance = comp, \temp_data[18] , temp_data[18], RAM, 1
instance = comp, \data[19]~I , data[19], RAM, 1
instance = comp, \temp_data[19] , temp_data[19], RAM, 1
instance = comp, \data[20]~I , data[20], RAM, 1
instance = comp, \temp_data[20] , temp_data[20], RAM, 1
instance = comp, \data[21]~I , data[21], RAM, 1
instance = comp, \temp_data[21] , temp_data[21], RAM, 1
instance = comp, \data[22]~I , data[22], RAM, 1
instance = comp, \temp_data[22] , temp_data[22], RAM, 1
instance = comp, \data[23]~I , data[23], RAM, 1
instance = comp, \temp_data[23] , temp_data[23], RAM, 1
instance = comp, \data[24]~I , data[24], RAM, 1
instance = comp, \temp_data[24] , temp_data[24], RAM, 1
instance = comp, \data[25]~I , data[25], RAM, 1
instance = comp, \temp_data[25] , temp_data[25], RAM, 1
instance = comp, \data[26]~I , data[26], RAM, 1
instance = comp, \temp_data[26] , temp_data[26], RAM, 1
instance = comp, \data[27]~I , data[27], RAM, 1
instance = comp, \temp_data[27] , temp_data[27], RAM, 1
instance = comp, \data[28]~I , data[28], RAM, 1
instance = comp, \temp_data[28] , temp_data[28], RAM, 1
instance = comp, \data[29]~I , data[29], RAM, 1
instance = comp, \temp_data[29] , temp_data[29], RAM, 1
instance = comp, \data[30]~I , data[30], RAM, 1
instance = comp, \temp_data[30] , temp_data[30], RAM, 1
instance = comp, \data[31]~I , data[31], RAM, 1
instance = comp, \temp_data[31] , temp_data[31], RAM, 1
instance = comp, \sel[0]~I , sel[0], RAM, 1
instance = comp, \sel[1]~I , sel[1], RAM, 1
instance = comp, \sel[2]~I , sel[2], RAM, 1
instance = comp, \q[0]~I , q[0], RAM, 1
instance = comp, \q[1]~I , q[1], RAM, 1
instance = comp, \q[2]~I , q[2], RAM, 1
instance = comp, \q[3]~I , q[3], RAM, 1
instance = comp, \q[4]~I , q[4], RAM, 1
instance = comp, \q[5]~I , q[5], RAM, 1
instance = comp, \q[6]~I , q[6], RAM, 1
instance = comp, \q[7]~I , q[7], RAM, 1
instance = comp, \q[8]~I , q[8], RAM, 1
instance = comp, \q[9]~I , q[9], RAM, 1
instance = comp, \q[10]~I , q[10], RAM, 1
instance = comp, \q[11]~I , q[11], RAM, 1
instance = comp, \q[12]~I , q[12], RAM, 1
instance = comp, \q[13]~I , q[13], RAM, 1
instance = comp, \q[14]~I , q[14], RAM, 1
instance = comp, \q[15]~I , q[15], RAM, 1
instance = comp, \q[16]~I , q[16], RAM, 1
instance = comp, \q[17]~I , q[17], RAM, 1
instance = comp, \q[18]~I , q[18], RAM, 1
instance = comp, \q[19]~I , q[19], RAM, 1
instance = comp, \q[20]~I , q[20], RAM, 1
instance = comp, \q[21]~I , q[21], RAM, 1
instance = comp, \q[22]~I , q[22], RAM, 1
instance = comp, \q[23]~I , q[23], RAM, 1
instance = comp, \q[24]~I , q[24], RAM, 1
instance = comp, \q[25]~I , q[25], RAM, 1
instance = comp, \q[26]~I , q[26], RAM, 1
instance = comp, \q[27]~I , q[27], RAM, 1
instance = comp, \q[28]~I , q[28], RAM, 1
instance = comp, \q[29]~I , q[29], RAM, 1
instance = comp, \q[30]~I , q[30], RAM, 1
instance = comp, \q[31]~I , q[31], RAM, 1