ram.vo

用VerilogHDL写的ram程序

// \q~369  = \en~combout  & (temp_data[24])

	.clk(\clk~combout ),
	.dataa(\en~combout ),
	.datab(vcc),
	.datac(\data~combout [24]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~369 ),
	.regout(temp_data[24]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[24] .lut_mask = "a0a0";
defparam \temp_data[24] .operation_mode = "normal";
defparam \temp_data[24] .output_mode = "comb_only";
defparam \temp_data[24] .register_cascade_mode = "off";
defparam \temp_data[24] .sum_lutc_input = "qfbk";
defparam \temp_data[24] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_W12
stratix_io \data[25]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [25]),
	.regout(),
	.ddioregout(),
	.padio(data[25]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[25]~I .ddio_mode = "none";
defparam \data[25]~I .input_async_reset = "none";
defparam \data[25]~I .input_power_up = "low";
defparam \data[25]~I .input_register_mode = "none";
defparam \data[25]~I .input_sync_reset = "none";
defparam \data[25]~I .oe_async_reset = "none";
defparam \data[25]~I .oe_power_up = "low";
defparam \data[25]~I .oe_register_mode = "none";
defparam \data[25]~I .oe_sync_reset = "none";
defparam \data[25]~I .operation_mode = "input";
defparam \data[25]~I .output_async_reset = "none";
defparam \data[25]~I .output_power_up = "low";
defparam \data[25]~I .output_register_mode = "none";
defparam \data[25]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X25_Y1_N0
stratix_lcell \temp_data[25] (
// Equation(s):
// \q~370  = \en~combout  & (temp_data[25])

	.clk(\clk~combout ),
	.dataa(\en~combout ),
	.datab(vcc),
	.datac(\data~combout [25]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~370 ),
	.regout(temp_data[25]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[25] .lut_mask = "a0a0";
defparam \temp_data[25] .operation_mode = "normal";
defparam \temp_data[25] .output_mode = "comb_only";
defparam \temp_data[25] .register_cascade_mode = "off";
defparam \temp_data[25] .sum_lutc_input = "qfbk";
defparam \temp_data[25] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_Y16
stratix_io \data[26]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [26]),
	.regout(),
	.ddioregout(),
	.padio(data[26]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[26]~I .ddio_mode = "none";
defparam \data[26]~I .input_async_reset = "none";
defparam \data[26]~I .input_power_up = "low";
defparam \data[26]~I .input_register_mode = "none";
defparam \data[26]~I .input_sync_reset = "none";
defparam \data[26]~I .oe_async_reset = "none";
defparam \data[26]~I .oe_power_up = "low";
defparam \data[26]~I .oe_register_mode = "none";
defparam \data[26]~I .oe_sync_reset = "none";
defparam \data[26]~I .operation_mode = "input";
defparam \data[26]~I .output_async_reset = "none";
defparam \data[26]~I .output_power_up = "low";
defparam \data[26]~I .output_register_mode = "none";
defparam \data[26]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X25_Y1_N9
stratix_lcell \temp_data[26] (
// Equation(s):
// \q~371  = \en~combout  & (temp_data[26])

	.clk(\clk~combout ),
	.dataa(\en~combout ),
	.datab(vcc),
	.datac(\data~combout [26]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~371 ),
	.regout(temp_data[26]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[26] .lut_mask = "a0a0";
defparam \temp_data[26] .operation_mode = "normal";
defparam \temp_data[26] .output_mode = "comb_only";
defparam \temp_data[26] .register_cascade_mode = "off";
defparam \temp_data[26] .sum_lutc_input = "qfbk";
defparam \temp_data[26] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AF18
stratix_io \data[27]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [27]),
	.regout(),
	.ddioregout(),
	.padio(data[27]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[27]~I .ddio_mode = "none";
defparam \data[27]~I .input_async_reset = "none";
defparam \data[27]~I .input_power_up = "low";
defparam \data[27]~I .input_register_mode = "none";
defparam \data[27]~I .input_sync_reset = "none";
defparam \data[27]~I .oe_async_reset = "none";
defparam \data[27]~I .oe_power_up = "low";
defparam \data[27]~I .oe_register_mode = "none";
defparam \data[27]~I .oe_sync_reset = "none";
defparam \data[27]~I .operation_mode = "input";
defparam \data[27]~I .output_async_reset = "none";
defparam \data[27]~I .output_power_up = "low";
defparam \data[27]~I .output_register_mode = "none";
defparam \data[27]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X25_Y1_N1
stratix_lcell \temp_data[27] (
// Equation(s):
// \q~372  = \en~combout  & (temp_data[27])

	.clk(\clk~combout ),
	.dataa(\en~combout ),
	.datab(vcc),
	.datac(\data~combout [27]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~372 ),
	.regout(temp_data[27]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[27] .lut_mask = "a0a0";
defparam \temp_data[27] .operation_mode = "normal";
defparam \temp_data[27] .output_mode = "comb_only";
defparam \temp_data[27] .register_cascade_mode = "off";
defparam \temp_data[27] .sum_lutc_input = "qfbk";
defparam \temp_data[27] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AD15
stratix_io \data[28]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [28]),
	.regout(),
	.ddioregout(),
	.padio(data[28]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[28]~I .ddio_mode = "none";
defparam \data[28]~I .input_async_reset = "none";
defparam \data[28]~I .input_power_up = "low";
defparam \data[28]~I .input_register_mode = "none";
defparam \data[28]~I .input_sync_reset = "none";
defparam \data[28]~I .oe_async_reset = "none";
defparam \data[28]~I .oe_power_up = "low";
defparam \data[28]~I .oe_register_mode = "none";
defparam \data[28]~I .oe_sync_reset = "none";
defparam \data[28]~I .operation_mode = "input";
defparam \data[28]~I .output_async_reset = "none";
defparam \data[28]~I .output_power_up = "low";
defparam \data[28]~I .output_register_mode = "none";
defparam \data[28]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X25_Y1_N2
stratix_lcell \temp_data[28] (
// Equation(s):
// \q~373  = \en~combout  & (temp_data[28])

	.clk(\clk~combout ),
	.dataa(\en~combout ),
	.datab(vcc),
	.datac(\data~combout [28]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~373 ),
	.regout(temp_data[28]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[28] .lut_mask = "a0a0";
defparam \temp_data[28] .operation_mode = "normal";
defparam \temp_data[28] .output_mode = "comb_only";
defparam \temp_data[28] .register_cascade_mode = "off";
defparam \temp_data[28] .sum_lutc_input = "qfbk";
defparam \temp_data[28] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AF11
stratix_io \data[29]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [29]),
	.regout(),
	.ddioregout(),
	.padio(data[29]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[29]~I .ddio_mode = "none";
defparam \data[29]~I .input_async_reset = "none";
defparam \data[29]~I .input_power_up = "low";
defparam \data[29]~I .input_register_mode = "none";
defparam \data[29]~I .input_sync_reset = "none";
defparam \data[29]~I .oe_async_reset = "none";
defparam \data[29]~I .oe_power_up = "low";
defparam \data[29]~I .oe_register_mode = "none";
defparam \data[29]~I .oe_sync_reset = "none";
defparam \data[29]~I .operation_mode = "input";
defparam \data[29]~I .output_async_reset = "none";
defparam \data[29]~I .output_power_up = "low";
defparam \data[29]~I .output_register_mode = "none";
defparam \data[29]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y1_N2
stratix_lcell \temp_data[29] (
// Equation(s):
// \q~374  = temp_data[29] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [29]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~374 ),
	.regout(temp_data[29]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[29] .lut_mask = "f000";
defparam \temp_data[29] .operation_mode = "normal";
defparam \temp_data[29] .output_mode = "comb_only";
defparam \temp_data[29] .register_cascade_mode = "off";
defparam \temp_data[29] .sum_lutc_input = "qfbk";
defparam \temp_data[29] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AA11
stratix_io \data[30]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [30]),
	.regout(),
	.ddioregout(),
	.padio(data[30]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[30]~I .ddio_mode = "none";
defparam \data[30]~I .input_async_reset = "none";
defparam \data[30]~I .input_power_up = "low";
defparam \data[30]~I .input_register_mode = "none";
defparam \data[30]~I .input_sync_reset = "none";
defparam \data[30]~I .oe_async_reset = "none";
defparam \data[30]~I .oe_power_up = "low";
defparam \data[30]~I .oe_register_mode = "none";
defparam \data[30]~I .oe_sync_reset = "none";
defparam \data[30]~I .operation_mode = "input";
defparam \data[30]~I .output_async_reset = "none";
defparam \data[30]~I .output_power_up = "low";
defparam \data[30]~I .output_register_mode = "none";
defparam \data[30]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y1_N4
stratix_lcell \temp_data[30] (
// Equation(s):
// \q~375  = temp_data[30] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [30]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~375 ),
	.regout(temp_data[30]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[30] .lut_mask = "f000";
defparam \temp_data[30] .operation_mode = "normal";
defparam \temp_data[30] .output_mode = "comb_only";
defparam \temp_data[30] .register_cascade_mode = "off";
defparam \temp_data[30] .sum_lutc_input = "qfbk";
defparam \temp_data[30] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AB17
stratix_io \data[31]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [31]),