ram.vo

用VerilogHDL写的ram程序

	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[17] .lut_mask = "f000";
defparam \temp_data[17] .operation_mode = "normal";
defparam \temp_data[17] .output_mode = "comb_only";
defparam \temp_data[17] .register_cascade_mode = "off";
defparam \temp_data[17] .sum_lutc_input = "qfbk";
defparam \temp_data[17] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_V27
stratix_io \data[18]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [18]),
	.regout(),
	.ddioregout(),
	.padio(data[18]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[18]~I .ddio_mode = "none";
defparam \data[18]~I .input_async_reset = "none";
defparam \data[18]~I .input_power_up = "low";
defparam \data[18]~I .input_register_mode = "none";
defparam \data[18]~I .input_sync_reset = "none";
defparam \data[18]~I .oe_async_reset = "none";
defparam \data[18]~I .oe_power_up = "low";
defparam \data[18]~I .oe_register_mode = "none";
defparam \data[18]~I .oe_sync_reset = "none";
defparam \data[18]~I .operation_mode = "input";
defparam \data[18]~I .output_async_reset = "none";
defparam \data[18]~I .output_power_up = "low";
defparam \data[18]~I .output_register_mode = "none";
defparam \data[18]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N4
stratix_lcell \temp_data[18] (
// Equation(s):
// \q~363  = temp_data[18] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [18]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~363 ),
	.regout(temp_data[18]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[18] .lut_mask = "f000";
defparam \temp_data[18] .operation_mode = "normal";
defparam \temp_data[18] .output_mode = "comb_only";
defparam \temp_data[18] .register_cascade_mode = "off";
defparam \temp_data[18] .sum_lutc_input = "qfbk";
defparam \temp_data[18] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_W28
stratix_io \data[19]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [19]),
	.regout(),
	.ddioregout(),
	.padio(data[19]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[19]~I .ddio_mode = "none";
defparam \data[19]~I .input_async_reset = "none";
defparam \data[19]~I .input_power_up = "low";
defparam \data[19]~I .input_register_mode = "none";
defparam \data[19]~I .input_sync_reset = "none";
defparam \data[19]~I .oe_async_reset = "none";
defparam \data[19]~I .oe_power_up = "low";
defparam \data[19]~I .oe_register_mode = "none";
defparam \data[19]~I .oe_sync_reset = "none";
defparam \data[19]~I .operation_mode = "input";
defparam \data[19]~I .output_async_reset = "none";
defparam \data[19]~I .output_power_up = "low";
defparam \data[19]~I .output_register_mode = "none";
defparam \data[19]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N2
stratix_lcell \temp_data[19] (
// Equation(s):
// \q~364  = temp_data[19] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [19]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~364 ),
	.regout(temp_data[19]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[19] .lut_mask = "f000";
defparam \temp_data[19] .operation_mode = "normal";
defparam \temp_data[19] .output_mode = "comb_only";
defparam \temp_data[19] .register_cascade_mode = "off";
defparam \temp_data[19] .sum_lutc_input = "qfbk";
defparam \temp_data[19] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AG15
stratix_io \data[20]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [20]),
	.regout(),
	.ddioregout(),
	.padio(data[20]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[20]~I .ddio_mode = "none";
defparam \data[20]~I .input_async_reset = "none";
defparam \data[20]~I .input_power_up = "low";
defparam \data[20]~I .input_register_mode = "none";
defparam \data[20]~I .input_sync_reset = "none";
defparam \data[20]~I .oe_async_reset = "none";
defparam \data[20]~I .oe_power_up = "low";
defparam \data[20]~I .oe_register_mode = "none";
defparam \data[20]~I .oe_sync_reset = "none";
defparam \data[20]~I .operation_mode = "input";
defparam \data[20]~I .output_async_reset = "none";
defparam \data[20]~I .output_power_up = "low";
defparam \data[20]~I .output_register_mode = "none";
defparam \data[20]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X25_Y1_N4
stratix_lcell \temp_data[20] (
// Equation(s):
// \q~365  = \en~combout  & (temp_data[20])

	.clk(\clk~combout ),
	.dataa(\en~combout ),
	.datab(vcc),
	.datac(\data~combout [20]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~365 ),
	.regout(temp_data[20]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[20] .lut_mask = "a0a0";
defparam \temp_data[20] .operation_mode = "normal";
defparam \temp_data[20] .output_mode = "comb_only";
defparam \temp_data[20] .register_cascade_mode = "off";
defparam \temp_data[20] .sum_lutc_input = "qfbk";
defparam \temp_data[20] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_Y17
stratix_io \data[21]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [21]),
	.regout(),
	.ddioregout(),
	.padio(data[21]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[21]~I .ddio_mode = "none";
defparam \data[21]~I .input_async_reset = "none";
defparam \data[21]~I .input_power_up = "low";
defparam \data[21]~I .input_register_mode = "none";
defparam \data[21]~I .input_sync_reset = "none";
defparam \data[21]~I .oe_async_reset = "none";
defparam \data[21]~I .oe_power_up = "low";
defparam \data[21]~I .oe_register_mode = "none";
defparam \data[21]~I .oe_sync_reset = "none";
defparam \data[21]~I .operation_mode = "input";
defparam \data[21]~I .output_async_reset = "none";
defparam \data[21]~I .output_power_up = "low";
defparam \data[21]~I .output_register_mode = "none";
defparam \data[21]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X25_Y1_N7
stratix_lcell \temp_data[21] (
// Equation(s):
// \q~366  = \en~combout  & (temp_data[21])

	.clk(\clk~combout ),
	.dataa(\en~combout ),
	.datab(vcc),
	.datac(\data~combout [21]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~366 ),
	.regout(temp_data[21]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[21] .lut_mask = "a0a0";
defparam \temp_data[21] .operation_mode = "normal";
defparam \temp_data[21] .output_mode = "comb_only";
defparam \temp_data[21] .register_cascade_mode = "off";
defparam \temp_data[21] .sum_lutc_input = "qfbk";
defparam \temp_data[21] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AD14
stratix_io \data[22]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [22]),
	.regout(),
	.ddioregout(),
	.padio(data[22]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[22]~I .ddio_mode = "none";
defparam \data[22]~I .input_async_reset = "none";
defparam \data[22]~I .input_power_up = "low";
defparam \data[22]~I .input_register_mode = "none";
defparam \data[22]~I .input_sync_reset = "none";
defparam \data[22]~I .oe_async_reset = "none";
defparam \data[22]~I .oe_power_up = "low";
defparam \data[22]~I .oe_register_mode = "none";
defparam \data[22]~I .oe_sync_reset = "none";
defparam \data[22]~I .operation_mode = "input";
defparam \data[22]~I .output_async_reset = "none";
defparam \data[22]~I .output_power_up = "low";
defparam \data[22]~I .output_register_mode = "none";
defparam \data[22]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X25_Y1_N8
stratix_lcell \temp_data[22] (
// Equation(s):
// \q~367  = \en~combout  & (temp_data[22])

	.clk(\clk~combout ),
	.dataa(\en~combout ),
	.datab(vcc),
	.datac(\data~combout [22]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~367 ),
	.regout(temp_data[22]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[22] .lut_mask = "a0a0";
defparam \temp_data[22] .operation_mode = "normal";
defparam \temp_data[22] .output_mode = "comb_only";
defparam \temp_data[22] .register_cascade_mode = "off";
defparam \temp_data[22] .sum_lutc_input = "qfbk";
defparam \temp_data[22] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AE4
stratix_io \data[23]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [23]),
	.regout(),
	.ddioregout(),
	.padio(data[23]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[23]~I .ddio_mode = "none";
defparam \data[23]~I .input_async_reset = "none";
defparam \data[23]~I .input_power_up = "low";
defparam \data[23]~I .input_register_mode = "none";
defparam \data[23]~I .input_sync_reset = "none";
defparam \data[23]~I .oe_async_reset = "none";
defparam \data[23]~I .oe_power_up = "low";
defparam \data[23]~I .oe_register_mode = "none";
defparam \data[23]~I .oe_sync_reset = "none";
defparam \data[23]~I .operation_mode = "input";
defparam \data[23]~I .output_async_reset = "none";
defparam \data[23]~I .output_power_up = "low";
defparam \data[23]~I .output_register_mode = "none";
defparam \data[23]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X25_Y1_N6
stratix_lcell \temp_data[23] (
// Equation(s):
// \q~368  = \en~combout  & (temp_data[23])

	.clk(\clk~combout ),
	.dataa(\en~combout ),
	.datab(vcc),
	.datac(\data~combout [23]),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~368 ),
	.regout(temp_data[23]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[23] .lut_mask = "a0a0";
defparam \temp_data[23] .operation_mode = "normal";
defparam \temp_data[23] .output_mode = "comb_only";
defparam \temp_data[23] .register_cascade_mode = "off";
defparam \temp_data[23] .sum_lutc_input = "qfbk";
defparam \temp_data[23] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_W13
stratix_io \data[24]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [24]),
	.regout(),
	.ddioregout(),
	.padio(data[24]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[24]~I .ddio_mode = "none";
defparam \data[24]~I .input_async_reset = "none";
defparam \data[24]~I .input_power_up = "low";
defparam \data[24]~I .input_register_mode = "none";
defparam \data[24]~I .input_sync_reset = "none";
defparam \data[24]~I .oe_async_reset = "none";
defparam \data[24]~I .oe_power_up = "low";
defparam \data[24]~I .oe_register_mode = "none";
defparam \data[24]~I .oe_sync_reset = "none";
defparam \data[24]~I .operation_mode = "input";
defparam \data[24]~I .output_async_reset = "none";
defparam \data[24]~I .output_power_up = "low";
defparam \data[24]~I .output_register_mode = "none";
defparam \data[24]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X25_Y1_N3
stratix_lcell \temp_data[24] (
// Equation(s):