ram.vo

用VerilogHDL写的ram程序

	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [11]),
	.regout(),
	.ddioregout(),
	.padio(data[11]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[11]~I .ddio_mode = "none";
defparam \data[11]~I .input_async_reset = "none";
defparam \data[11]~I .input_power_up = "low";
defparam \data[11]~I .input_register_mode = "none";
defparam \data[11]~I .input_sync_reset = "none";
defparam \data[11]~I .oe_async_reset = "none";
defparam \data[11]~I .oe_power_up = "low";
defparam \data[11]~I .oe_register_mode = "none";
defparam \data[11]~I .oe_sync_reset = "none";
defparam \data[11]~I .operation_mode = "input";
defparam \data[11]~I .output_async_reset = "none";
defparam \data[11]~I .output_power_up = "low";
defparam \data[11]~I .output_register_mode = "none";
defparam \data[11]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N7
stratix_lcell \temp_data[11] (
// Equation(s):
// \q~356  = temp_data[11] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [11]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~356 ),
	.regout(temp_data[11]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[11] .lut_mask = "f000";
defparam \temp_data[11] .operation_mode = "normal";
defparam \temp_data[11] .output_mode = "comb_only";
defparam \temp_data[11] .register_cascade_mode = "off";
defparam \temp_data[11] .sum_lutc_input = "qfbk";
defparam \temp_data[11] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_Y26
stratix_io \data[12]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [12]),
	.regout(),
	.ddioregout(),
	.padio(data[12]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[12]~I .ddio_mode = "none";
defparam \data[12]~I .input_async_reset = "none";
defparam \data[12]~I .input_power_up = "low";
defparam \data[12]~I .input_register_mode = "none";
defparam \data[12]~I .input_sync_reset = "none";
defparam \data[12]~I .oe_async_reset = "none";
defparam \data[12]~I .oe_power_up = "low";
defparam \data[12]~I .oe_register_mode = "none";
defparam \data[12]~I .oe_sync_reset = "none";
defparam \data[12]~I .operation_mode = "input";
defparam \data[12]~I .output_async_reset = "none";
defparam \data[12]~I .output_power_up = "low";
defparam \data[12]~I .output_register_mode = "none";
defparam \data[12]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N8
stratix_lcell \temp_data[12] (
// Equation(s):
// \q~357  = temp_data[12] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [12]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~357 ),
	.regout(temp_data[12]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[12] .lut_mask = "f000";
defparam \temp_data[12] .operation_mode = "normal";
defparam \temp_data[12] .output_mode = "comb_only";
defparam \temp_data[12] .register_cascade_mode = "off";
defparam \temp_data[12] .sum_lutc_input = "qfbk";
defparam \temp_data[12] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_W25
stratix_io \data[13]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [13]),
	.regout(),
	.ddioregout(),
	.padio(data[13]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[13]~I .ddio_mode = "none";
defparam \data[13]~I .input_async_reset = "none";
defparam \data[13]~I .input_power_up = "low";
defparam \data[13]~I .input_register_mode = "none";
defparam \data[13]~I .input_sync_reset = "none";
defparam \data[13]~I .oe_async_reset = "none";
defparam \data[13]~I .oe_power_up = "low";
defparam \data[13]~I .oe_register_mode = "none";
defparam \data[13]~I .oe_sync_reset = "none";
defparam \data[13]~I .operation_mode = "input";
defparam \data[13]~I .output_async_reset = "none";
defparam \data[13]~I .output_power_up = "low";
defparam \data[13]~I .output_register_mode = "none";
defparam \data[13]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N1
stratix_lcell \temp_data[13] (
// Equation(s):
// \q~358  = temp_data[13] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [13]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~358 ),
	.regout(temp_data[13]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[13] .lut_mask = "f000";
defparam \temp_data[13] .operation_mode = "normal";
defparam \temp_data[13] .output_mode = "comb_only";
defparam \temp_data[13] .register_cascade_mode = "off";
defparam \temp_data[13] .sum_lutc_input = "qfbk";
defparam \temp_data[13] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_V25
stratix_io \data[14]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [14]),
	.regout(),
	.ddioregout(),
	.padio(data[14]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[14]~I .ddio_mode = "none";
defparam \data[14]~I .input_async_reset = "none";
defparam \data[14]~I .input_power_up = "low";
defparam \data[14]~I .input_register_mode = "none";
defparam \data[14]~I .input_sync_reset = "none";
defparam \data[14]~I .oe_async_reset = "none";
defparam \data[14]~I .oe_power_up = "low";
defparam \data[14]~I .oe_register_mode = "none";
defparam \data[14]~I .oe_sync_reset = "none";
defparam \data[14]~I .operation_mode = "input";
defparam \data[14]~I .output_async_reset = "none";
defparam \data[14]~I .output_power_up = "low";
defparam \data[14]~I .output_register_mode = "none";
defparam \data[14]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N5
stratix_lcell \temp_data[14] (
// Equation(s):
// \q~359  = temp_data[14] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [14]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~359 ),
	.regout(temp_data[14]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[14] .lut_mask = "f000";
defparam \temp_data[14] .operation_mode = "normal";
defparam \temp_data[14] .output_mode = "comb_only";
defparam \temp_data[14] .register_cascade_mode = "off";
defparam \temp_data[14] .sum_lutc_input = "qfbk";
defparam \temp_data[14] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_T25
stratix_io \data[15]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [15]),
	.regout(),
	.ddioregout(),
	.padio(data[15]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[15]~I .ddio_mode = "none";
defparam \data[15]~I .input_async_reset = "none";
defparam \data[15]~I .input_power_up = "low";
defparam \data[15]~I .input_register_mode = "none";
defparam \data[15]~I .input_sync_reset = "none";
defparam \data[15]~I .oe_async_reset = "none";
defparam \data[15]~I .oe_power_up = "low";
defparam \data[15]~I .oe_register_mode = "none";
defparam \data[15]~I .oe_sync_reset = "none";
defparam \data[15]~I .operation_mode = "input";
defparam \data[15]~I .output_async_reset = "none";
defparam \data[15]~I .output_power_up = "low";
defparam \data[15]~I .output_register_mode = "none";
defparam \data[15]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N6
stratix_lcell \temp_data[15] (
// Equation(s):
// \q~360  = temp_data[15] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [15]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~360 ),
	.regout(temp_data[15]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[15] .lut_mask = "f000";
defparam \temp_data[15] .operation_mode = "normal";
defparam \temp_data[15] .output_mode = "comb_only";
defparam \temp_data[15] .register_cascade_mode = "off";
defparam \temp_data[15] .sum_lutc_input = "qfbk";
defparam \temp_data[15] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_W26
stratix_io \data[16]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [16]),
	.regout(),
	.ddioregout(),
	.padio(data[16]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[16]~I .ddio_mode = "none";
defparam \data[16]~I .input_async_reset = "none";
defparam \data[16]~I .input_power_up = "low";
defparam \data[16]~I .input_register_mode = "none";
defparam \data[16]~I .input_sync_reset = "none";
defparam \data[16]~I .oe_async_reset = "none";
defparam \data[16]~I .oe_power_up = "low";
defparam \data[16]~I .oe_register_mode = "none";
defparam \data[16]~I .oe_sync_reset = "none";
defparam \data[16]~I .operation_mode = "input";
defparam \data[16]~I .output_async_reset = "none";
defparam \data[16]~I .output_power_up = "low";
defparam \data[16]~I .output_register_mode = "none";
defparam \data[16]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N0
stratix_lcell \temp_data[16] (
// Equation(s):
// \q~361  = temp_data[16] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [16]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~361 ),
	.regout(temp_data[16]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[16] .lut_mask = "f000";
defparam \temp_data[16] .operation_mode = "normal";
defparam \temp_data[16] .output_mode = "comb_only";
defparam \temp_data[16] .register_cascade_mode = "off";
defparam \temp_data[16] .sum_lutc_input = "qfbk";
defparam \temp_data[16] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_U21
stratix_io \data[17]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [17]),
	.regout(),
	.ddioregout(),
	.padio(data[17]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[17]~I .ddio_mode = "none";
defparam \data[17]~I .input_async_reset = "none";
defparam \data[17]~I .input_power_up = "low";
defparam \data[17]~I .input_register_mode = "none";
defparam \data[17]~I .input_sync_reset = "none";
defparam \data[17]~I .oe_async_reset = "none";
defparam \data[17]~I .oe_power_up = "low";
defparam \data[17]~I .oe_register_mode = "none";
defparam \data[17]~I .oe_sync_reset = "none";
defparam \data[17]~I .operation_mode = "input";
defparam \data[17]~I .output_async_reset = "none";
defparam \data[17]~I .output_power_up = "low";
defparam \data[17]~I .output_register_mode = "none";
defparam \data[17]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N9
stratix_lcell \temp_data[17] (
// Equation(s):
// \q~362  = temp_data[17] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [17]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~362 ),
	.regout(temp_data[17]),
	.cout(),