ram.vo

用VerilogHDL写的ram程序

defparam \data[4]~I .output_register_mode = "none";
defparam \data[4]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N1
stratix_lcell \temp_data[4] (
// Equation(s):
// \q~349  = temp_data[4] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [4]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~349 ),
	.regout(temp_data[4]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[4] .lut_mask = "f000";
defparam \temp_data[4] .operation_mode = "normal";
defparam \temp_data[4] .output_mode = "comb_only";
defparam \temp_data[4] .register_cascade_mode = "off";
defparam \temp_data[4] .sum_lutc_input = "qfbk";
defparam \temp_data[4] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AB11
stratix_io \data[5]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [5]),
	.regout(),
	.ddioregout(),
	.padio(data[5]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[5]~I .ddio_mode = "none";
defparam \data[5]~I .input_async_reset = "none";
defparam \data[5]~I .input_power_up = "low";
defparam \data[5]~I .input_register_mode = "none";
defparam \data[5]~I .input_sync_reset = "none";
defparam \data[5]~I .oe_async_reset = "none";
defparam \data[5]~I .oe_power_up = "low";
defparam \data[5]~I .oe_register_mode = "none";
defparam \data[5]~I .oe_sync_reset = "none";
defparam \data[5]~I .operation_mode = "input";
defparam \data[5]~I .output_async_reset = "none";
defparam \data[5]~I .output_power_up = "low";
defparam \data[5]~I .output_register_mode = "none";
defparam \data[5]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N2
stratix_lcell \temp_data[5] (
// Equation(s):
// \q~350  = temp_data[5] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [5]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~350 ),
	.regout(temp_data[5]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[5] .lut_mask = "f000";
defparam \temp_data[5] .operation_mode = "normal";
defparam \temp_data[5] .output_mode = "comb_only";
defparam \temp_data[5] .register_cascade_mode = "off";
defparam \temp_data[5] .sum_lutc_input = "qfbk";
defparam \temp_data[5] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_F12
stratix_io \data[6]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [6]),
	.regout(),
	.ddioregout(),
	.padio(data[6]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[6]~I .ddio_mode = "none";
defparam \data[6]~I .input_async_reset = "none";
defparam \data[6]~I .input_power_up = "low";
defparam \data[6]~I .input_register_mode = "none";
defparam \data[6]~I .input_sync_reset = "none";
defparam \data[6]~I .oe_async_reset = "none";
defparam \data[6]~I .oe_power_up = "low";
defparam \data[6]~I .oe_register_mode = "none";
defparam \data[6]~I .oe_sync_reset = "none";
defparam \data[6]~I .operation_mode = "input";
defparam \data[6]~I .output_async_reset = "none";
defparam \data[6]~I .output_power_up = "low";
defparam \data[6]~I .output_register_mode = "none";
defparam \data[6]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N3
stratix_lcell \temp_data[6] (
// Equation(s):
// \q~351  = temp_data[6] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [6]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~351 ),
	.regout(temp_data[6]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[6] .lut_mask = "f000";
defparam \temp_data[6] .operation_mode = "normal";
defparam \temp_data[6] .output_mode = "comb_only";
defparam \temp_data[6] .register_cascade_mode = "off";
defparam \temp_data[6] .sum_lutc_input = "qfbk";
defparam \temp_data[6] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_K11
stratix_io \data[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [7]),
	.regout(),
	.ddioregout(),
	.padio(data[7]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[7]~I .ddio_mode = "none";
defparam \data[7]~I .input_async_reset = "none";
defparam \data[7]~I .input_power_up = "low";
defparam \data[7]~I .input_register_mode = "none";
defparam \data[7]~I .input_sync_reset = "none";
defparam \data[7]~I .oe_async_reset = "none";
defparam \data[7]~I .oe_power_up = "low";
defparam \data[7]~I .oe_register_mode = "none";
defparam \data[7]~I .oe_sync_reset = "none";
defparam \data[7]~I .operation_mode = "input";
defparam \data[7]~I .output_async_reset = "none";
defparam \data[7]~I .output_power_up = "low";
defparam \data[7]~I .output_register_mode = "none";
defparam \data[7]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N4
stratix_lcell \temp_data[7] (
// Equation(s):
// \q~352  = temp_data[7] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [7]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~352 ),
	.regout(temp_data[7]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[7] .lut_mask = "f000";
defparam \temp_data[7] .operation_mode = "normal";
defparam \temp_data[7] .output_mode = "comb_only";
defparam \temp_data[7] .register_cascade_mode = "off";
defparam \temp_data[7] .sum_lutc_input = "qfbk";
defparam \temp_data[7] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_W10
stratix_io \data[8]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [8]),
	.regout(),
	.ddioregout(),
	.padio(data[8]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[8]~I .ddio_mode = "none";
defparam \data[8]~I .input_async_reset = "none";
defparam \data[8]~I .input_power_up = "low";
defparam \data[8]~I .input_register_mode = "none";
defparam \data[8]~I .input_sync_reset = "none";
defparam \data[8]~I .oe_async_reset = "none";
defparam \data[8]~I .oe_power_up = "low";
defparam \data[8]~I .oe_register_mode = "none";
defparam \data[8]~I .oe_sync_reset = "none";
defparam \data[8]~I .operation_mode = "input";
defparam \data[8]~I .output_async_reset = "none";
defparam \data[8]~I .output_power_up = "low";
defparam \data[8]~I .output_register_mode = "none";
defparam \data[8]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N5
stratix_lcell \temp_data[8] (
// Equation(s):
// \q~353  = temp_data[8] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [8]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~353 ),
	.regout(temp_data[8]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[8] .lut_mask = "f000";
defparam \temp_data[8] .operation_mode = "normal";
defparam \temp_data[8] .output_mode = "comb_only";
defparam \temp_data[8] .register_cascade_mode = "off";
defparam \temp_data[8] .sum_lutc_input = "qfbk";
defparam \temp_data[8] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_T7
stratix_io \data[9]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [9]),
	.regout(),
	.ddioregout(),
	.padio(data[9]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[9]~I .ddio_mode = "none";
defparam \data[9]~I .input_async_reset = "none";
defparam \data[9]~I .input_power_up = "low";
defparam \data[9]~I .input_register_mode = "none";
defparam \data[9]~I .input_sync_reset = "none";
defparam \data[9]~I .oe_async_reset = "none";
defparam \data[9]~I .oe_power_up = "low";
defparam \data[9]~I .oe_register_mode = "none";
defparam \data[9]~I .oe_sync_reset = "none";
defparam \data[9]~I .operation_mode = "input";
defparam \data[9]~I .output_async_reset = "none";
defparam \data[9]~I .output_power_up = "low";
defparam \data[9]~I .output_register_mode = "none";
defparam \data[9]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N9
stratix_lcell \temp_data[9] (
// Equation(s):
// \q~354  = temp_data[9] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [9]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~354 ),
	.regout(temp_data[9]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[9] .lut_mask = "f000";
defparam \temp_data[9] .operation_mode = "normal";
defparam \temp_data[9] .output_mode = "comb_only";
defparam \temp_data[9] .register_cascade_mode = "off";
defparam \temp_data[9] .sum_lutc_input = "qfbk";
defparam \temp_data[9] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_Y27
stratix_io \data[10]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [10]),
	.regout(),
	.ddioregout(),
	.padio(data[10]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[10]~I .ddio_mode = "none";
defparam \data[10]~I .input_async_reset = "none";
defparam \data[10]~I .input_power_up = "low";
defparam \data[10]~I .input_register_mode = "none";
defparam \data[10]~I .input_sync_reset = "none";
defparam \data[10]~I .oe_async_reset = "none";
defparam \data[10]~I .oe_power_up = "low";
defparam \data[10]~I .oe_register_mode = "none";
defparam \data[10]~I .oe_sync_reset = "none";
defparam \data[10]~I .operation_mode = "input";
defparam \data[10]~I .output_async_reset = "none";
defparam \data[10]~I .output_power_up = "low";
defparam \data[10]~I .output_register_mode = "none";
defparam \data[10]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X1_Y6_N3
stratix_lcell \temp_data[10] (
// Equation(s):
// \q~355  = temp_data[10] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [10]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~355 ),
	.regout(temp_data[10]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[10] .lut_mask = "f000";
defparam \temp_data[10] .operation_mode = "normal";
defparam \temp_data[10] .output_mode = "comb_only";
defparam \temp_data[10] .register_cascade_mode = "off";
defparam \temp_data[10] .sum_lutc_input = "qfbk";
defparam \temp_data[10] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_U22
stratix_io \data[11]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),