ram.vo

用VerilogHDL写的ram程序

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

// DATE "12/12/2008 23:04:53"

// 
// Device: Altera EP1S10F780C6 Package FBGA780
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module RAM (
	clk,
	data,
	sel,
	en,
	q);
input 	clk;
input 	[31:0] data;
input 	[2:0] sel;
input 	en;
output 	[31:0] q;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("RAM_v.sdo");
// synopsys translate_on

wire \clk~combout ;
wire \en~combout ;
wire \q~345 ;
wire \q~346 ;
wire \q~347 ;
wire \q~348 ;
wire \q~349 ;
wire \q~350 ;
wire \q~351 ;
wire \q~352 ;
wire \q~353 ;
wire \q~354 ;
wire \q~355 ;
wire \q~356 ;
wire \q~357 ;
wire \q~358 ;
wire \q~359 ;
wire \q~360 ;
wire \q~361 ;
wire \q~362 ;
wire \q~363 ;
wire \q~364 ;
wire \q~365 ;
wire \q~366 ;
wire \q~367 ;
wire \q~368 ;
wire \q~369 ;
wire \q~370 ;
wire \q~371 ;
wire \q~372 ;
wire \q~373 ;
wire \q~374 ;
wire \q~375 ;
wire \q~376 ;
wire [31:0] \data~combout ;
wire [31:0] temp_data;


// atom is at PIN_R25
stratix_io \clk~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.ddioregout(),
	.padio(clk),
	.dqsundelayedout());
// synopsys translate_off
defparam \clk~I .ddio_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .oe_power_up = "low";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .operation_mode = "input";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J12
stratix_io \data[0]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [0]),
	.regout(),
	.ddioregout(),
	.padio(data[0]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[0]~I .ddio_mode = "none";
defparam \data[0]~I .input_async_reset = "none";
defparam \data[0]~I .input_power_up = "low";
defparam \data[0]~I .input_register_mode = "none";
defparam \data[0]~I .input_sync_reset = "none";
defparam \data[0]~I .oe_async_reset = "none";
defparam \data[0]~I .oe_power_up = "low";
defparam \data[0]~I .oe_register_mode = "none";
defparam \data[0]~I .oe_sync_reset = "none";
defparam \data[0]~I .operation_mode = "input";
defparam \data[0]~I .output_async_reset = "none";
defparam \data[0]~I .output_power_up = "low";
defparam \data[0]~I .output_register_mode = "none";
defparam \data[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_V18
stratix_io \en~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\en~combout ),
	.regout(),
	.ddioregout(),
	.padio(en),
	.dqsundelayedout());
// synopsys translate_off
defparam \en~I .ddio_mode = "none";
defparam \en~I .input_async_reset = "none";
defparam \en~I .input_power_up = "low";
defparam \en~I .input_register_mode = "none";
defparam \en~I .input_sync_reset = "none";
defparam \en~I .oe_async_reset = "none";
defparam \en~I .oe_power_up = "low";
defparam \en~I .oe_register_mode = "none";
defparam \en~I .oe_sync_reset = "none";
defparam \en~I .operation_mode = "input";
defparam \en~I .output_async_reset = "none";
defparam \en~I .output_power_up = "low";
defparam \en~I .output_register_mode = "none";
defparam \en~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N8
stratix_lcell \temp_data[0] (
// Equation(s):
// \q~345  = temp_data[0] # !\en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [0]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~345 ),
	.regout(temp_data[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[0] .lut_mask = "f0ff";
defparam \temp_data[0] .operation_mode = "normal";
defparam \temp_data[0] .output_mode = "comb_only";
defparam \temp_data[0] .register_cascade_mode = "off";
defparam \temp_data[0] .sum_lutc_input = "qfbk";
defparam \temp_data[0] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_T20
stratix_io \data[1]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [1]),
	.regout(),
	.ddioregout(),
	.padio(data[1]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[1]~I .ddio_mode = "none";
defparam \data[1]~I .input_async_reset = "none";
defparam \data[1]~I .input_power_up = "low";
defparam \data[1]~I .input_register_mode = "none";
defparam \data[1]~I .input_sync_reset = "none";
defparam \data[1]~I .oe_async_reset = "none";
defparam \data[1]~I .oe_power_up = "low";
defparam \data[1]~I .oe_register_mode = "none";
defparam \data[1]~I .oe_sync_reset = "none";
defparam \data[1]~I .operation_mode = "input";
defparam \data[1]~I .output_async_reset = "none";
defparam \data[1]~I .output_power_up = "low";
defparam \data[1]~I .output_register_mode = "none";
defparam \data[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N7
stratix_lcell \temp_data[1] (
// Equation(s):
// \q~346  = temp_data[1] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [1]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~346 ),
	.regout(temp_data[1]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[1] .lut_mask = "f000";
defparam \temp_data[1] .operation_mode = "normal";
defparam \temp_data[1] .output_mode = "comb_only";
defparam \temp_data[1] .register_cascade_mode = "off";
defparam \temp_data[1] .sum_lutc_input = "qfbk";
defparam \temp_data[1] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AC11
stratix_io \data[2]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [2]),
	.regout(),
	.ddioregout(),
	.padio(data[2]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[2]~I .ddio_mode = "none";
defparam \data[2]~I .input_async_reset = "none";
defparam \data[2]~I .input_power_up = "low";
defparam \data[2]~I .input_register_mode = "none";
defparam \data[2]~I .input_sync_reset = "none";
defparam \data[2]~I .oe_async_reset = "none";
defparam \data[2]~I .oe_power_up = "low";
defparam \data[2]~I .oe_register_mode = "none";
defparam \data[2]~I .oe_sync_reset = "none";
defparam \data[2]~I .operation_mode = "input";
defparam \data[2]~I .output_async_reset = "none";
defparam \data[2]~I .output_power_up = "low";
defparam \data[2]~I .output_register_mode = "none";
defparam \data[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N6
stratix_lcell \temp_data[2] (
// Equation(s):
// \q~347  = temp_data[2] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [2]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~347 ),
	.regout(temp_data[2]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[2] .lut_mask = "f000";
defparam \temp_data[2] .operation_mode = "normal";
defparam \temp_data[2] .output_mode = "comb_only";
defparam \temp_data[2] .register_cascade_mode = "off";
defparam \temp_data[2] .sum_lutc_input = "qfbk";
defparam \temp_data[2] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_U4
stratix_io \data[3]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [3]),
	.regout(),
	.ddioregout(),
	.padio(data[3]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[3]~I .ddio_mode = "none";
defparam \data[3]~I .input_async_reset = "none";
defparam \data[3]~I .input_power_up = "low";
defparam \data[3]~I .input_register_mode = "none";
defparam \data[3]~I .input_sync_reset = "none";
defparam \data[3]~I .oe_async_reset = "none";
defparam \data[3]~I .oe_power_up = "low";
defparam \data[3]~I .oe_register_mode = "none";
defparam \data[3]~I .oe_sync_reset = "none";
defparam \data[3]~I .operation_mode = "input";
defparam \data[3]~I .output_async_reset = "none";
defparam \data[3]~I .output_power_up = "low";
defparam \data[3]~I .output_register_mode = "none";
defparam \data[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X33_Y10_N0
stratix_lcell \temp_data[3] (
// Equation(s):
// \q~348  = temp_data[3] & \en~combout 

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\data~combout [3]),
	.datad(\en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\q~348 ),
	.regout(temp_data[3]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \temp_data[3] .lut_mask = "f000";
defparam \temp_data[3] .operation_mode = "normal";
defparam \temp_data[3] .output_mode = "comb_only";
defparam \temp_data[3] .register_cascade_mode = "off";
defparam \temp_data[3] .sum_lutc_input = "qfbk";
defparam \temp_data[3] .synch_mode = "on";
// synopsys translate_on

// atom is at PIN_AE10
stratix_io \data[4]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data~combout [4]),
	.regout(),
	.ddioregout(),
	.padio(data[4]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data[4]~I .ddio_mode = "none";
defparam \data[4]~I .input_async_reset = "none";
defparam \data[4]~I .input_power_up = "low";
defparam \data[4]~I .input_register_mode = "none";
defparam \data[4]~I .input_sync_reset = "none";
defparam \data[4]~I .oe_async_reset = "none";
defparam \data[4]~I .oe_power_up = "low";
defparam \data[4]~I .oe_register_mode = "none";
defparam \data[4]~I .oe_sync_reset = "none";
defparam \data[4]~I .operation_mode = "input";
defparam \data[4]~I .output_async_reset = "none";
defparam \data[4]~I .output_power_up = "low";