vote_1.v

来自「三人投票程序」· Verilog 代码 · 共 20 行

module vote_1(pass,vote[11:1]);
    input vote[11:1];
    output pass;
    integer count=1,i;
    for(i=1;i<=11;i=i+1)
       begin
        if(vote[i]=1)
          begin 
           count=count+1;
          end
    end
    if(count>=6)
       begin 
        pass=1;
       end
    else
       begin 
        pass=0;
       end
endmodule