connect.tcl

来自「fpga从FIFO读数据并上传到双口ram中。」· TCL 代码 · 共 43 行

# Created by Libero IDE 6.2.50.1
# Sat Mar 07 16:38:12 2009

# (NEW DESIGN)

# create a new design
new_design -name "connect" -family "PA"

# set default back-annotation base-name
set_defvar "BA_NAME" "connect_ba"

# set working directory
set_defvar "DESDIR" "C:/Actelprj/connect20090223/designer/impl1"

# set back-annotation output directory
set_defvar "BA_DIR" "C:/Actelprj/connect20090223/designer/impl1"

# enable the export back-annotation netlist
set_defvar "BA_NETLIST_ALSO" "1"

# set EDIF options
set_defvar "EDNINFLAVOR" "GENERIC"

# set HDL options
set_defvar "NETLIST_NAMING_STYLE" "VHDL93"

# setup status report options
set_defvar "EXPORT_STATUS_REPORT" "1"
set_defvar "EXPORT_STATUS_REPORT_FILENAME" "connect.rpt"

# legacy audit-mode flags (left here for historical reasons)
set_defvar "AUDIT_NETLIST_FILE" "1"
set_defvar "AUDIT_DCF_FILE" "1"
set_defvar "AUDIT_PIN_FILE" "1"
set_defvar "AUDIT_ADL_FILE" "1"

# import of input files
import_source  \
-format "edif" -edif_flavor "GENERIC" -netlist_naming "VHDL" {../../synthesis/connect.edn}

# export translation of original netlist
export -format "vhdl" {../../synthesis/connect.vhd}