designer_genhdl.log

来自「fpga从FIFO读数据并上传到双口ram中。」· LOG 代码 · 共 26 行

Created a new design.
'BA_NAME' set to 'connect_ba'
'DESDIR' set to 'C:/Actelprj/connect20090223/designer/impl1'
'BA_DIR' set to 'C:/Actelprj/connect20090223/designer/impl1'
'BA_NETLIST_ALSO' set to '1'
'EDNINFLAVOR' set to 'GENERIC'
'NETLIST_NAMING_STYLE' set to 'VHDL93'
'EXPORT_STATUS_REPORT' set to '1'
'EXPORT_STATUS_REPORT_FILENAME' set to 'connect.rpt'
'AUDIT_NETLIST_FILE' set to '1'
'AUDIT_DCF_FILE' set to '1'
'AUDIT_PIN_FILE' set to '1'
'AUDIT_ADL_FILE' set to '1'
Imported the file:
   C:\Actelprj\connect20090223\synthesis\connect.edn

The Import command succeeded ( 00:00:02 )
Wrote to the file: ..\..\synthesis\connect.vhd

The Export command succeeded ( 00:00:01 )

The Execute Script command succeeded ( 00:00:07 )
Warning: The database was closed without a save, modifications are lost [OK]
Design closed.