connect.vhd

fpga从FIFO读数据并上传到双口ram中。

-- connect.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity connect is
port( inclk: in std_logic;
      inrst: in std_logic;
--fifo
      ffs :    in  std_logic; 
      hfs:    in  std_logic;
      datains:   in  std_logic_vector(7 downto 0); 

      sc_ds:   in  std_logic;--data or control data
      rdys:    in   std_logic;
 
      bstns :  out std_logic;--set 1 the 8\10b trans
      rfs:     out  std_logic; --reframe ,set 1 to find k28.5
      fifows:    out std_logic; --write enable
      fifors :   out std_logic;
      mrs:       out std_logic;--mr

--dpram
      dataouts: out std_logic_vector(31 downto 0);
   
      ads: out std_logic_vector(14 downto 0);
      ces: out std_logic;
      rws : out std_logic;

      oes: out std_logic;
      bms:  out std_logic;
      sizes:  out std_logic;
      semps: out std_logic);
end;

architecture one of connect is
--fifo_r
component fifo_r is
 port( rst:      in  std_logic;
      clk :     in  std_logic;

                                                                                                                                                                                                                                                                                                                                                                      
      ff :    in  std_logic; 
      hf :    in  std_logic;
      datain:   in  std_logic_vector(7 downto 0); 

      sc_d:   in  std_logic;--data or control data
      rdy:    in   std_logic;
 
      bstn :  out std_logic;--set 1 the 8\10b trans
      rf:     out  std_logic; --reframe ,set 1 to find k28.5
      fifow:    out std_logic; --write enable
      fifor :   out std_logic;
      mr:       out std_logic;--mr
      dataout:  out std_logic_vector(31 downto 0);

      comunif:out std_logic);

    
end component fifo_r;

--dpram_w
component dpram_w is
port(
     clk:   in std_logic;
     rst:   in std_logic;
     datain:in std_logic_vector(31 downto 0);
     comuni: in std_logic;--设置一个FPGA和DPRAM通信的口

   
     ad: out std_logic_vector(14 downto 0);
     ce: out std_logic;
     rw : out std_logic;

     dataout: out std_logic_vector(31 downto 0);
 
     oe: out std_logic;
     bm:  out std_logic;
     size:  out std_logic;
     semp: out std_logic );
end component dpram_w;

signal data_connect:std_logic_vector(31 downto 0);
signal comuni_connect:std_logic;

begin
 
fiforr: fifo_r port map(rst=>inrst,
                      clk=>inclk ,                                                                                                                                                                                                                                                                                                                                                        
                      ff=>ffs,
                      hf=>hfs,
                      datain=>datains,
                      sc_d=>sc_ds,
                      rdy =>rdys,
                      bstn=>bstns, 
                      rf=>rfs,
                      fifow=>fifows,
                      fifor=>fifors,
                      mr=>mrs,
                      dataout=>data_connect,
                      comunif=>comuni_connect);


dpram: dpram_w port map( clk=>inclk,
                         rst=>inrst,
                         datain=>data_connect,
                         comuni=>comuni_connect,
                         ad=>ads,
                         ce=>ces,
                         rw=>rws,
                         dataout=>dataouts,
                         oe=>oes,
                         bm=>bms,
                         size=>sizes,
                         semp=>semps);
end one;