fifo_r.vhd

fpga从FIFO读数据并上传到双口ram中。

-- fifo_r.-- fifo_r.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fifo_r is
 port( rst:      in  std_logic;
      clk :     in  std_logic;

                                                                                                                                                                                                                                                                                                                                                                      
          ff :    in  std_logic; 
      hf :    in  std_logic;
      datain:   in  std_logic_vector(7 downto 0); 

      sc_d:   in  std_logic;--data or control data
      rdy:    in   std_logic;
 
      bstn :  out std_logic;--set 1 the 8\10b trans
      rf:     out  std_logic; --reframe ,set 1 to find k28.5
      fifow:    out std_logic; --write enable
      fifor :   out std_logic;
      mr:       out std_logic;--mr
      dataout:  out std_logic_vector(31 downto 0);

      comunif:out std_logic);

     
      --f_ef:     in  std_logic;
      --f_rvs:    in  std_logic;
      --f_ckr:    in  std_logic; 

end fifo_r;

architecture one of fifo_r is
type state is(s0,s01,s001,s1,s2,s3,check1,check20,check21,reading,reading0,passout);

signal cur_state: state;
signal mr_temp :std_logic;
signal data_temp: std_logic_vector(7 downto 0);
signal fdata_temp: std_logic_vector(31 downto 0);

signal byte_count:std_logic_vector(7 downto 0);---188个字节
signal flag_count: std_logic_vector(1 downto 0);--3个0x47
signal data_count: std_logic_vector(11 downto 0);---2048个字节

signal word_count:std_logic_vector(1 downto 0);--4个字节是32位

signal flag:std_logic;--数据输入正确，可以输出

begin 
process(clk,rst,hf,ff)is 
begin
if rst='0' then cur_state<=s0;
                mr_temp<='0';
                fifor<='1';
                data_temp<=(others=>'0');
                fdata_temp<=(others=>'0');
                byte_count<=(others=>'0');
                flag_count<=(others=>'0');
                data_count<=(others=>'0');
                word_count<=(others=>'0');
                flag<='0';
                dataout<=(others=>'0');
                comunif<='1';
elsif rising_edge(clk) then
                       case(cur_state)is
                       when s0=>mr_temp<='1'; cur_state<=s01;
                       when s01=>if ff='0' then cur_state<=s001;
                                                mr_temp<='0';

                                 end if;
                          --s0等待asi准备好，以ff信号为标志
                       when s001=>mr_temp<='1'; cur_state<=s1;
                       when s1=>if hf='0' then cur_state<=s2;
                                end if;
                       when s2=>fifor<='0';cur_state<=s3;
                       when s3=>fifor<='1';
                                data_temp<=datain;
                                if flag='1' then cur_state<=reading;
                                else if data_temp="01000111" then flag_count<=flag_count+1;
                                                                  byte_count<=byte_count+1;
                                                                  cur_state<=check1;
                                     else flag_count<=(others=>'0');
                                          cur_state<=s2;
                                     end if;
                                end if;
                      when check1=>fifor<='0' ;
                                   cur_state<=check20;
                      when check20=>fifor<='1';
                                    if byte_count=188
                                    then byte_count<=(others=>'0');
                                         data_temp<=datain;
                                         cur_state<=check21;
                                    else cur_state<=check1;
                                         byte_count<=byte_count+1;
                                    end if;   
                      when check21=> if data_temp="0100111"
                                    then if flag_count=2 then  cur_state<=reading;
                                                               flag<='1';
                                                               flag_count<=(others=>'0');
                                          else flag_count<=flag_count+1;cur_state<=check1;
                                          end if;
                                     else  flag_count<=(others=>'0');
                                           cur_state<=s2;
                                     end if;
                      when reading=> cur_state<=reading0;
                                     fdata_temp<=data_temp&fdata_temp(31 downto 8);
                                     word_count<=word_count+1;
                                     data_count<=data_count+1;
                      when reading0=> if word_count="00" then cur_state<=passout;
                                      else cur_state<=s2;
                                      end if;
                      when passout=>  dataout<=fdata_temp;
                                      comunif<='0';
                                      if data_count=2048 then 
                                                         flag<='0';
                                                         cur_state<=s1;
                                                         data_count<=(others=>'0');
                                                         comunif<='1';
                                     else cur_state<=s2;
                                     end if;
                      end case;
end if;
end process;
rf<='1';
mr<=mr_temp;
bstn<='1';
fifow<='1' when mr_temp='0' else rdy or sc_d;
end one;