dpram_w.vhd

fpga从FIFO读数据并上传到双口ram中。

-- dpram_w.vhd
-- dpram_w.vhd


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dpram_w is
port(
     clk:   in std_logic;
     rst:   in std_logic;
     datain:in std_logic_vector(31 downto 0);
     comuni: in std_logic;--设置一个FPGA和DPRAM通信的口

   
     ad: out std_logic_vector(14 downto 0);
     ce: out std_logic;
     rw : out std_logic;

     dataout: out std_logic_vector(31 downto 0);
 
     oe: out std_logic;
     bm:  out std_logic;
     size:  out std_logic;
     semp: out std_logic );
end dpram_w;



architecture one of dpram_w is

type state is(s0,s1,s2,s3,mail1,mail2,mail3,mail4,mail5);

signal cur_state: state;
signal ad_temp:std_logic_vector(14 downto 0);
signal datain_temp:std_logic_vector(31 downto 0);
signal data_count:std_logic_vector(5 downto 0 );
signal data_temp:std_logic_vector(31 downto 0);



signal ad_tt:std_logic_vector(14 downto 0 );


---读入11个ts包，因为11*188=2068，刚好为2K

begin

process(clk,rst)is 
begin
 if rst='0' 
 then cur_state<=s0;
      ad_temp<=(others=>'0');
	  ad_tt<=(others=>'0');
      ce<='1';
      rw<='1';
      data_count<=(others=>'0');
	  dataout<=(others=>'0');
	  ad<=(others=>'0');
	  data_temp<=(others=>'0');
	  datain_temp<=(others=>'0');



 else if rising_edge(clk)
      then case(cur_state)is
       when s0=> if comuni='1' 
                 then cur_state<=s1;
                      if ad_temp=x"EAF"
                      then ad_temp<=(others=>'0');
                                
                 end if;
				 end if;
       when s1=> cur_state<=s2;
                 ad<=ad_temp;
                 datain_temp<=datain;
                 ce<='0';

       when s2=>cur_state<=s3; 
                rw<='0';
                dataout<=datain_temp;
               
  
       when s3=> ce<='1';
                 rw<='1';
                if ad_temp=516 or ad_temp=1033---地址设置不对，待改
                then
                 ad_tt<="111111111111110";
                 cur_state<=mail1;
                else
                 cur_state<=s0;
                 ad_temp<=ad_temp+1;
                 end if;

       when mail1=> cur_state<=mail2;
                   if ad_temp=516
                   then   data_temp<="00000000000000000000000000000001";
                   else data_temp<=(others=>'0');    
                   end if;  
       when mail2=>cur_state<=mail3;
                   ce<='0';
                   ad<=ad_tt;
       when mail3=>cur_state<=mail4;
                   dataout<=data_temp;
                   rw<='0';
       when mail4=>cur_state<=mail5;
                   ce<='1';
                   rw<='1';
       when mail5=>cur_state<=s0;
	  
	   end case;
end if;
end if;
end process;

oe<='1';
bm<='0';
size<='0';
semp<='1';
end one;