stdout.log

fpga从FIFO读数据并上传到双口ram中。

License checkout: synplify_pc

Starting:    C:\Libero\Synplify\Synplify_81A\bin\mbin\synplify.exe
Install:     C:\Libero\Synplify\Synplify_81A
Date:        Sat Mar 07 16:38:00 2009
Version:     8.1A

Version 8.1A

Arguments:   connect_syn.prj
ProductType: synplify

License: synplify_pc node-locked 



Running synthesis on connect_syn:synthesis

log file: "C:\Actelprj\connect20090223\synthesis\connect.srr"


Running Vhdl Compiler...

Vhdl Compiler Completed


Vhdl Compiler: 0 errors, 44 warnings, 7 notes - from log file C:\Actelprj\connect20090223\synthesis\connect.srr


Running PA Mapper...

PA Mapper Completed


PA Mapper: 0 errors, 0 warnings, 2 notes - from log file C:\Actelprj\connect20090223\synthesis\connect.srr


Total: 0 errors, 44 warnings, 10 notes

exit status=0