connect.vhd

fpga从FIFO读数据并上传到双口ram中。

        \inrst_c_i_0_9\, Q => \cur_state[8]_net_1\);
    
    \dataout[18]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_21\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[18]\);
    
    \ad_temp[5]\ : DFFC
      port map(CLK => inclk_c, D => \ad_temp_6[5]\, CLR => 
        inrst_c_i_0_17, Q => \ad_temp[5]_net_1\);
    
    datain_temp_68 : MUX2H
      port map(A => \datain_temp[16]_net_1\, B => 
        data_connect(16), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_68\);
    
    \ad_temp[11]\ : DFFC
      port map(CLK => inclk_c, D => \ad_temp_6[11]\, CLR => 
        inrst_c_i_0, Q => \ad_temp[11]_net_1\);
    
    un1_ad_temp_2_I_91 : AND2
      port map(A => \ad_temp[12]_net_1\, B => \ad_temp[13]_net_1\, 
        Y => \DWACT_ADD_CI_0_pog_array_1_5[0]\);
    
    \ad_4[2]\ : MUX2H
      port map(A => \ad_tt[1]_net_1\, B => \ad_temp[2]_net_1\, S
         => \cur_state[7]_net_1\, Y => \ad_4[2]_net_1\);
    
    datain_temp_75 : MUX2H
      port map(A => \datain_temp[23]_net_1\, B => 
        data_connect(23), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_75\);
    
    \datain_temp[3]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_55\, CLR => 
        inrst_c_i_0_10, Q => \datain_temp[3]_net_1\);
    
    un1_ad_temp_2_G_1_0_4 : AND3
      port map(A => \G_1_0_0\, B => G_1_0_1_0, C => \G_1_1\, Y
         => G_1_0_4);
    
    \datain_temp[10]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_62\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[10]_net_1\);
    
    \dataout_4[6]\ : MUX2H
      port map(A => \data_temp[1]_net_1\, B => 
        \datain_temp[6]_net_1\, S => \cur_state[6]_net_1\, Y => 
        \dataout_4[6]_net_1\);
    
    \dataout_4[29]\ : MUX2H
      port map(A => \data_temp_0[1]_net_1\, B => 
        \datain_temp[29]_net_1\, S => \cur_state_0[6]_net_1\, Y
         => \dataout_4[29]_net_1\);
    
    dataout_22 : MUX2H
      port map(A => \dataout_4[19]_net_1\, B => \dataouts_c[19]\, 
        S => N_230_1, Y => \dataout_22\);
    
    datain_temp_64 : MUX2H
      port map(A => \datain_temp[12]_net_1\, B => 
        data_connect(12), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_64\);
    
    \ad[6]\ : DFFC
      port map(CLK => inclk_c, D => \ad_41\, CLR => 
        inrst_c_i_0_13_0, Q => \ads_c[6]\);
    
    ad_temp_0_sqmuxa_1 : NAND3FTT
      port map(A => \ad_temp[14]_net_1\, B => comuni_connect, C
         => \cur_state[8]_net_1\, Y => ad_temp_0_sqmuxa_1_i);
    
    \ad_temp[6]\ : DFFC
      port map(CLK => inclk_c, D => I_49_0, CLR => inrst_c_i_0_17, 
        Q => \ad_temp_i_0_i[6]\);
    
    \dataout_4[18]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[18]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[18]_net_1\);
    
    ad_35 : MUX2H
      port map(A => \ad_4[0]_net_1\, B => \ads_c[0]\, S => 
        \un1_cur_state_2_i_a2\, Y => \ad_35\);
    
    \ad_tt_0[1]\ : DFFC
      port map(CLK => inclk_c, D => \ad_tt_1_84\, CLR => 
        inrst_c_i_0_9_0, Q => \ad_tt_0[1]_net_1\);
    
    \ad_temp_6[10]\ : AND2
      port map(A => ad_temp_0_sqmuxa_i_0, B => I_51, Y => 
        \ad_temp_6[10]_net_1\);
    
    dataout_12 : MUX2H
      port map(A => \dataout_4[9]_net_1\, B => \dataouts_c[9]\, S
         => N_230_1, Y => \dataout_12\);
    
    \ad[9]\ : DFFC
      port map(CLK => inclk_c, D => \ad_44\, CLR => 
        inrst_c_i_0_13_0, Q => \ads_c[9]\);
    
    \dataout_4[1]\ : MUX2H
      port map(A => \data_temp[1]_net_1\, B => 
        \datain_temp[1]_net_1\, S => \cur_state[6]_net_1\, Y => 
        \dataout_4[1]_net_1\);
    
    un1_ad_temp_2_G_1_0_0 : AND2
      port map(A => \DWACT_ADD_CI_0_pog_array_1[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_1[0]\, Y => \G_1_0_1\);
    
    \dataout_4[20]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[20]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[20]_net_1\);
    
    data_temp_50 : MUX2H
      port map(A => \data_temp[0]_net_1\, B => \un9_ad_temp_i\, S
         => \cur_state[4]_net_1\, Y => \data_temp_50\);
    
    \dataout_4[13]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[13]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[13]_net_1\);
    
    un1_ad_temp_2_I_52 : XOR2
      port map(A => \ad_temp[2]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_52);
    
    dataout_21 : MUX2H
      port map(A => \dataout_4[18]_net_1\, B => \dataouts_c[18]\, 
        S => N_230_1, Y => \dataout_21\);
    
    \ad_4[11]\ : MUX2H
      port map(A => \ad_tt_0[1]_net_1\, B => \ad_temp[11]_net_1\, 
        S => \cur_state_3[7]_net_1\, Y => \ad_4[11]_net_1\);
    
    un1_ad_temp_2_G_1_0_1 : AND2
      port map(A => \DWACT_ADD_CI_0_pog_array_1[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_3[0]\, Y => G_1_0_1_1);
    
    ad_36 : MUX2H
      port map(A => \ad_4[1]_net_1\, B => \ads_c[1]\, S => 
        \un1_cur_state_2_i_a2\, Y => \ad_36\);
    
    un1_ad_temp_2_G_1_2_3 : AND3
      port map(A => G_1_2_2, B => 
        \DWACT_ADD_CI_0_pog_array_1_3[0]\, C => 
        \ad_temp[0]_net_1\, Y => G_1_2_3);
    
    un1_ad_temp_2_G_1_1_0 : XOR2
      port map(A => \ad_temp[14]_net_1\, B => \G_4\, Y => 
        G_1_1_0_0);
    
    \ad_temp[8]\ : DFFC
      port map(CLK => inclk_c, D => I_57, CLR => inrst_c_i_0_17, 
        Q => \ad_temp[8]_net_1\);
    
    ad_39 : MUX2H
      port map(A => \ad_4[4]_net_1\, B => \ads_c[4]\, S => 
        \un1_cur_state_2_i_a2\, Y => \ad_39\);
    
    dataout_11 : MUX2H
      port map(A => \dataout_4[8]_net_1\, B => \dataouts_c[8]\, S
         => N_230_1, Y => \dataout_11\);
    
    G_2_0_2 : NAND3FFT
      port map(A => G_2_0_0_i, B => un14_ad_temp_1_i, C => 
        \ad_temp[0]_net_1\, Y => G_2_0_2_i);
    
    \dataout_4[31]\ : MUX2H
      port map(A => \data_temp_0[1]_net_1\, B => 
        \datain_temp[31]_net_1\, S => \cur_state_0[6]_net_1\, Y
         => \dataout_4[31]_net_1\);
    
    \ad_4[4]\ : MUX2H
      port map(A => \ad_tt[1]_net_1\, B => \ad_temp[4]_net_1\, S
         => \cur_state_3[7]_net_1\, Y => \ad_4[4]_net_1\);
    
    dataout_26 : MUX2H
      port map(A => \dataout_4[23]_net_1\, B => \dataouts_c[23]\, 
        S => N_230_0, Y => \dataout_26\);
    
    un1_cur_state_2_i_a2_0 : NOR2
      port map(A => \cur_state[3]_net_1\, B => 
        \cur_state_0[7]_net_1\, Y => N_229_0);
    
    \dataout[16]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_19\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[16]\);
    
    G_1_2_0 : NAND3
      port map(A => \G_3_0_i_a3\, B => \G_2\, C => 
        \cur_state[5]_net_1\, Y => ad_tt_1_sqmuxa);
    
    G_1_0 : NAND2
      port map(A => ad_temp_0_sqmuxa_i_0, B => ad_tt_1_sqmuxa, Y
         => \G_1_0_0\);
    
    \cur_state_ns_0_a2[1]\ : AND2
      port map(A => comuni_connect, B => \cur_state[8]_net_1\, Y
         => \cur_state_ns[1]\);
    
    un1_ad_temp_2_I_49 : XOR2
      port map(A => \ad_temp_i_0_i[6]\, B => 
        \DWACT_ADD_CI_0_g_array_11[0]\, Y => I_49_0);
    
    un1_ad_temp_2_I_87 : AND2
      port map(A => \ad_temp_i_0_i[6]\, B => \ad_temp[7]_net_1\, 
        Y => \DWACT_ADD_CI_0_pog_array_1_2[0]\);
    
    dataout_16 : MUX2H
      port map(A => \dataout_4[13]_net_1\, B => \dataouts_c[13]\, 
        S => N_230_1, Y => \dataout_16\);
    
    \ad_4[1]\ : MUX2H
      port map(A => \ad_tt[1]_net_1\, B => \ad_temp[1]_net_1\, S
         => \cur_state[7]_net_1\, Y => \ad_4[1]_net_1\);
    
    dataout_25 : MUX2H
      port map(A => \dataout_4[22]_net_1\, B => \dataouts_c[22]\, 
        S => N_230_0, Y => \dataout_25\);
    
    \dataout[8]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_11\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[8]\);
    
    datain_temp_52 : MUX2H
      port map(A => \datain_temp[0]_net_1\, B => data_connect(0), 
        S => \cur_state_2[7]_net_1\, Y => \datain_temp_52\);
    
    dataout_32 : MUX2H
      port map(A => \dataout_4[29]_net_1\, B => \dataouts_c[29]\, 
        S => N_230_0, Y => \dataout_32\);
    
    dataout_3 : MUX2H
      port map(A => \dataout_4[0]_net_1\, B => \dataouts_c[0]\, S
         => \un1_cur_state_i_a2\, Y => \dataout_3\);
    
    un1_ad_temp_2_I_92 : AND2
      port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_2[0]\, Y => 
        \DWACT_ADD_CI_0_pog_array_2[0]\);
    
    un1_ad_temp_2_G_0 : AND2
      port map(A => \ad_temp[0]_net_1\, B => \ad_temp[1]_net_1\, 
        Y => \G_0\);
    
    \dataout[19]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_22\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[19]\);
    
    un1_ad_temp_2_I_56 : XOR2
      port map(A => \ad_temp[1]_net_1\, B => 
        \DWACT_ADD_CI_0_TMP[0]\, Y => I_56);
    
    \dataout_4[11]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[11]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[11]_net_1\);
    
    \datain_temp[7]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_59\, CLR => 
        inrst_c_i_0_10, Q => \datain_temp[7]_net_1\);
    
    dataout_15 : MUX2H
      port map(A => \dataout_4[12]_net_1\, B => \dataouts_c[12]\, 
        S => N_230_1, Y => \dataout_15\);
    
    \ad_4[3]\ : MUX2H
      port map(A => \ad_tt[1]_net_1\, B => \ad_temp[3]_net_1\, S
         => \cur_state[7]_net_1\, Y => \ad_4[3]_net_1\);
    
    ad_48 : MUX2H
      port map(A => \ad_4[13]_net_1\, B => \ads_c[13]\, S => 
        N_229_0, Y => \ad_48\);
    
    \ad_4[7]\ : MUX2H
      port map(A => \ad_tt[1]_net_1\, B => \ad_temp[7]_net_1\, S
         => \cur_state_3[7]_net_1\, Y => \ad_4[7]_net_1\);
    
    \ad_temp_i_0_2[14]\ : INV
      port map(A => inrst_c, Y => inrst_c_i_0_2);
    
    \datain_temp[28]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_80\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[28]_net_1\);
    
    \datain_temp[11]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_63\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[11]_net_1\);
    
    datain_temp_77 : MUX2H
      port map(A => \datain_temp[25]_net_1\, B => 
        data_connect(25), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_77\);
    
    \cur_state_2[7]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state_ns[1]\, CLR => 
        inrst_c_i_0_9_0, Q => \cur_state_2[7]_net_1\);
    
    dataout_31 : MUX2H
      port map(A => \dataout_4[28]_net_1\, B => \dataouts_c[28]\, 
        S => N_230_0, Y => \dataout_31\);
    
    ad_42 : MUX2H
      port map(A => \ad_4[7]_net_1\, B => \ads_c[7]\, S => 
        N_229_0, Y => \ad_42\);
    
    \datain_temp[19]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_71\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[19]_net_1\);
    
    datain_temp_71 : MUX2H
      port map(A => \datain_temp[19]_net_1\, B => 
        data_connect(19), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_71\);
    
    G_1_0_0 : OR2
      port map(A => \ad_temp[10]_net_1\, B => \ad_temp[12]_net_1\, 
        Y => G_1_i);
    
    \ad_4[6]\ : MUX2H
      port map(A => \ad_tt[1]_net_1\, B => \ad_temp_i_0_i[6]\, S
         => \cur_state_3[7]_net_1\, Y => \ad_4[6]_net_1\);
    
    datain_temp_53 : MUX2H
      port map(A => \datain_temp[1]_net_1\, B => data_connect(1), 
        S => \cur_state_2[7]_net_1\, Y => \datain_temp_53\);
    
    \ad[5]\ : DFFC
      port map(CLK => inclk_c, D => \ad_40\, CLR => 
        inrst_c_i_0_13_0, Q => \ads_c[5]\);
    
    \datain_temp[1]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_53\, CLR => 
        inrst_c_i_0_10, Q => \datain_temp[1]_net_1\);
    
    un9_ad_temp_i : INV
      port map(A => \G_2\, Y => \un9_ad_temp_i\);
    
    G_1_3 : AND2FT
      port map(A => \un1_ad_temp_2_i[6]\, B => 
        ad_temp_0_sqmuxa_i_0, Y => \ad_temp_6[5]\);
    
    \ad[7]\ : DFFC
      port map(CLK => inclk_c, D => \ad_42\, CLR => 
        inrst_c_i_0_13_0, Q => \ads_c[7]\);
    
    datain_temp_62 : MUX2H
      port map(A => \datain_temp[10]_net_1\, B => 
        data_connect(10), S => \cur_state_2[7]_net_1\, Y => 
        \datain_temp_62\);
    
    \ad_temp[0]\ : DFFC
      port map(CLK => inclk_c, D => 
        \DWACT_ADD_CI_0_partial_sum[0]\, CLR => inrst_c_i_0_17, Q
         => \ad_temp[0]_net_1\);
    
    \dataout[25]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_28\, CLR => 
        inrst_c_i_