connect.vhd

fpga从FIFO读数据并上传到双口ram中。

      port map(A => \dataout_4[6]_net_1\, B => \dataouts_c[6]\, S
         => \un1_cur_state_i_a2\, Y => \dataout_9\);
    
    \ad_temp_i_0_1[14]\ : INV
      port map(A => inrst_c, Y => inrst_c_i_0_1);
    
    \ad[12]\ : DFFC
      port map(CLK => inclk_c, D => \ad_47\, CLR => 
        inrst_c_i_0_14, Q => \ads_c[12]\);
    
    G_1_1 : AND2FT
      port map(A => \un1_ad_temp_2_i_i_0_i[10]\, B => 
        ad_temp_0_sqmuxa_i_0, Y => \ad_temp_6[9]\);
    
    \ad_temp_i_0_9[14]\ : INV
      port map(A => inrst_c, Y => \inrst_c_i_0_9\);
    
    un1_cur_state_2_i_a2 : NOR2
      port map(A => \cur_state[3]_net_1\, B => 
        \cur_state[7]_net_1\, Y => \un1_cur_state_2_i_a2\);
    
    G_2_2_0 : OR2
      port map(A => \ad_temp[7]_net_1\, B => \ad_temp[5]_net_1\, 
        Y => G_2_2_0_0);
    
    un1_ad_temp_2_G_1_5 : AND3
      port map(A => \G_1_0_0\, B => \G_1\, C => \G_1_1\, Y => 
        \DWACT_ADD_CI_0_g_array_10[0]\);
    
    \dataout_4[4]\ : MUX2H
      port map(A => \data_temp[1]_net_1\, B => 
        \datain_temp[4]_net_1\, S => \cur_state[6]_net_1\, Y => 
        \dataout_4[4]_net_1\);
    
    \dataout_4[21]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[21]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[21]_net_1\);
    
    \dataout[24]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_27\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[24]\);
    
    \dataout[31]\ : DFFC
      port map(CLK => inclk_c, D => dataout_34_0, CLR => 
        inrst_c_i_0_17, Q => \dataouts_c[31]\);
    
    rw_2 : AO21
      port map(A => \rws_c\, B => \un1_cur_state_i_a2\, C => 
        \un1_cur_state_1_i_a2\, Y => \rw_2\);
    
    ce_1 : AO21
      port map(A => \ces_c\, B => \un1_cur_state_2_i_a2\, C => 
        \un1_cur_state_1_i_a2\, Y => \ce_1\);
    
    \ad_tt[1]\ : DFFC
      port map(CLK => inclk_c, D => \ad_tt_1_84\, CLR => 
        \inrst_c_i_0_9\, Q => \ad_tt[1]_net_1\);
    
    \data_temp_0[1]\ : DFFC
      port map(CLK => inclk_c, D => \data_temp_51\, CLR => 
        inrst_c_i_0_13_0, Q => \data_temp_0[1]_net_1\);
    
    \datain_temp[20]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_72\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[20]_net_1\);
    
    \ad_temp_i_0_4[14]\ : INV
      port map(A => inrst_c, Y => inrst_c_i_0_4);
    
    datain_temp_69 : MUX2H
      port map(A => \datain_temp[17]_net_1\, B => 
        data_connect(17), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_69\);
    
    \datain_temp[0]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_52\, CLR => 
        inrst_c_i_0_10, Q => \datain_temp[0]_net_1\);
    
    ad_temp_0_sqmuxa_9 : OR3
      port map(A => un9_ad_temp_7_i_i, B => \ad_temp_i_0_i[6]\, C
         => \ad_temp[8]_net_1\, Y => ad_temp_0_sqmuxa_9_i);
    
    \ad[13]\ : DFFC
      port map(CLK => inclk_c, D => \ad_48\, CLR => 
        inrst_c_i_0_14, Q => \ads_c[13]\);
    
    \dataout_4[16]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[16]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[16]_net_1\);
    
    dataout_20 : MUX2H
      port map(A => \dataout_4[17]_net_1\, B => \dataouts_c[17]\, 
        S => N_230_1, Y => \dataout_20\);
    
    un14_ad_temp_1 : OR2
      port map(A => \ad_temp[4]_net_1\, B => \ad_temp[2]_net_1\, 
        Y => un14_ad_temp_1_i);
    
    \datain_temp[15]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_67\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[15]_net_1\);
    
    \ad_temp_i_0_5[14]\ : INV
      port map(A => inrst_c, Y => inrst_c_i_0_5);
    
    \ad_4[12]\ : MUX2H
      port map(A => \ad_tt_0[1]_net_1\, B => \ad_temp[12]_net_1\, 
        S => \cur_state_3[7]_net_1\, Y => \ad_4[12]_net_1\);
    
    un1_ad_temp_2_I_86 : AND2
      port map(A => \ad_temp[4]_net_1\, B => \ad_temp[5]_net_1\, 
        Y => \DWACT_ADD_CI_0_pog_array_1_1[0]\);
    
    un1_ad_temp_2_G_3 : AND3
      port map(A => \G_1_0_0\, B => \G_1_0\, C => \G_0\, Y => G_3);
    
    dataout_10 : MUX2H
      port map(A => \dataout_4[7]_net_1\, B => \dataouts_c[7]\, S
         => \un1_cur_state_i_a2\, Y => \dataout_10\);
    
    \ad[14]\ : DFFC
      port map(CLK => inclk_c, D => \ad_49\, CLR => 
        inrst_c_i_0_14, Q => \ads_c[14]\);
    
    \cur_state_1[7]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state_ns[1]\, CLR => 
        inrst_c_i_0_9_0, Q => \cur_state_1[7]_net_1\);
    
    \datain_temp[8]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_60\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[8]_net_1\);
    
    \dataout_4[12]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[12]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[12]_net_1\);
    
    \dataout[15]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_18\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[15]\);
    
    un1_ad_temp_2_G_2_1 : AND3
      port map(A => \G_1_0_0\, B => \ad_temp[0]_net_1\, C => 
        \ad_temp[1]_net_1\, Y => \DWACT_ADD_CI_0_g_array_1[0]\);
    
    \ad_temp[10]\ : DFFC
      port map(CLK => inclk_c, D => \ad_temp_6[10]_net_1\, CLR
         => inrst_c_i_0_17, Q => \ad_temp[10]_net_1\);
    
    \datain_temp[16]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_68\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[16]_net_1\);
    
    \cur_state_0[6]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state[7]_net_1\, CLR => 
        inrst_c_i_0_9_0, Q => \cur_state_0[6]_net_1\);
    
    un1_ad_temp_2_G_1_0_3 : XOR2FT
      port map(A => \ad_temp[7]_net_1\, B => G_3, Y => 
        \un1_ad_temp_2_i[8]\);
    
    un1_ad_temp_2_G_1_2_0 : AND3
      port map(A => \DWACT_ADD_CI_0_pog_array_1[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_1[0]\, C => 
        \ad_temp_i_0_i[6]\, Y => \G_1_0\);
    
    \datain_temp[12]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_64\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[12]_net_1\);
    
    ad_temp_0_sqmuxa_6 : AND2
      port map(A => \ad_temp[2]_net_1\, B => \ad_temp[3]_net_1\, 
        Y => \ad_temp_0_sqmuxa_6\);
    
    G_1_0_1 : NAND2FT
      port map(A => \ad_temp[1]_net_1\, B => \ad_temp[10]_net_1\, 
        Y => N_26_i);
    
    \dataout[27]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_30\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[27]\);
    
    \ad_temp_i_0_12[14]\ : INV
      port map(A => inrst_c_0, Y => inrst_c_i_0_12);
    
    \dataout[4]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_7\, CLR => 
        inrst_c_i_0_14, Q => \dataouts_c[4]\);
    
    datain_temp_81 : MUX2H
      port map(A => \datain_temp[29]_net_1\, B => 
        data_connect(29), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_81\);
    
    dataout_29 : MUX2H
      port map(A => \dataout_4[26]_net_1\, B => \dataouts_c[26]\, 
        S => N_230_0, Y => \dataout_29\);
    
    \cur_state[3]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state[4]_net_1\, CLR => 
        inrst_c_i_0_10, Q => \cur_state[3]_net_1\);
    
    \dataout[11]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_14\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[11]\);
    
    datain_temp_72 : MUX2H
      port map(A => \datain_temp[20]_net_1\, B => 
        data_connect(20), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_72\);
    
    \dataout[12]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_15\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[12]\);
    
    ce : DFFS
      port map(CLK => inclk_c, D => \ce_1\, SET => 
        \inrst_c_i_0_9\, Q => \ces_c\);
    
    data_temp_51 : AND2FT
      port map(A => \cur_state[4]_net_1\, B => 
        \data_temp_0[1]_net_1\, Y => \data_temp_51\);
    
    dataout_8 : MUX2H
      port map(A => \dataout_4[5]_net_1\, B => \dataouts_c[5]\, S
         => \un1_cur_state_i_a2\, Y => \dataout_8\);
    
    \dataout_4[0]\ : MUX2H
      port map(A => \data_temp[0]_net_1\, B => 
        \datain_temp[0]_net_1\, S => \cur_state[6]_net_1\, Y => 
        \dataout_4[0]_net_1\);
    
    datain_temp_58 : MUX2H
      port map(A => \datain_temp[6]_net_1\, B => data_connect(6), 
        S => \cur_state_2[7]_net_1\, Y => \datain_temp_58\);
    
    \ad[11]\ : DFFC
      port map(CLK => inclk_c, D => \ad_46\, CLR => 
        inrst_c_i_0_14, Q => \ads_c[11]\);
    
    ad_temp_0_sqmuxa : OR3
      port map(A => ad_temp_0_sqmuxa_12_i, B => 
        ad_temp_0_sqmuxa_10_i, C => ad_temp_0_sqmuxa_11_i, Y => 
        ad_temp_0_sqmuxa_i_0);
    
    un1_ad_temp_2_G_1_7 : XOR2
      port map(A => \G_2_2\, B => \ad_temp[9]_net_1\, Y => 
        \un1_ad_temp_2_i_i_0_i[10]\);
    
    un1_ad_temp_2_G_1_2_1 : XOR2
      port map(A => \ad_temp[13]_net_1\, B => G_1_0_4, Y => 
        G_1_2_1);
    
    dataout_30 : MUX2H
      port map(A => \dataout_4[27]_net_1\, B => \dataouts_c[27]\, 
        S => N_230_0, Y => \dataout_30\);
    
    un1_ad_temp_2_I_90 : AND2
      port map(A => \DWACT_ADD_CI_0_pog_array_1_3[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_1_4[0]\, Y => 
        \DWACT_ADD_CI_0_pog_array_2_1[0]\);
    
    un1_ad_temp_2_I_51 : XOR2
      port map(A => \ad_temp[10]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_11_1[0]\, Y => I_51);
    
    dataout_19 : MUX2H
      port map(A => \dataout_4[16]_net_1\, B => \dataouts_c[16]\, 
        S => N_230_1, Y => \dataout_19\);
    
    un1_ad_temp_2_I_36 : XOR2
      port map(A => \ad_temp[0]_net_1\, B => \G_1_0_0\, Y => 
        \DWACT_ADD_CI_0_partial_sum[0]\);
    
    ad_38 : MUX2H
      port map(A => \ad_4[3]_net_1\, B => \ads_c[3]\, S => 
        \un1_cur_state_2_i_a2\, Y => \ad_38\);
    
    \ad_temp_i_0_3[14]\ : INV
      port map(A => inrst_c, Y => inrst_c_i_0_3);
    
    un1_ad_temp_2_I_55 : XOR2
      port map(A => \ad_temp[12]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_10[0]\, Y => I_55);
    
    datain_temp_54 : MUX2H
      port map(A => \datain_temp[2]_net_1\, B => data_connect(2), 
        S => \cur_state_2[7]_net_1\, Y => \datain_temp_54\);
    
    \datain_temp[21]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_73\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[21]_net_1\);
    
    un1_ad_temp_2_G_1_0_6 : AND2
      port map(A => \ad_temp[1]_net_1\, B => \ad_temp[2]_net_1\, 
        Y => G_1_0_6);
    
    un1_ad_temp_2_G_4 : AND3
      port map(A => \G_1_0_0\, B => G_1_3_0, C => \G_1_1\, Y => 
        \G_4\);
    
    \dataout[9]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_12\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[9]\);
    
    \cur_state_i[1]\ : INV
      port map(A => \cur_state[1]_net_1\, Y => 
        \cur_state_i[1]_net_1\);
    
    \ad_temp[4]\ : DFFC
      port map(CLK => inclk_c, D => \ad_temp_6[4]_net_1\, CLR => 
        inrst_c_i_0_17, Q => \ad_temp[4]_net_1\);
    
    \ad_temp[14]\ : DFFC
      port map(CLK => inclk_c, D => G_1_1_0_0, CLR => inrst_c_i_0, 
        Q => \ad_temp[14]_net_1\);
    
    \dataout_4[25]\ : MUX2H
      port map(A => \data_temp_0[1]_net_1\, B => 
        \datain_temp[25]_net_1\, S => \cur_state_0[6]_net_1\, Y
         => \dataout_4[25]_net_1\);
    
    \dataout[13]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_16\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[13]\);
    
    \datain_temp[29]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_81\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[29]_net_1\);
    
    un1_ad_temp_2_G_1_3_0 : AND3
      port map(A => \DWACT_ADD_CI_0_pog_array_2[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_2_1[0]\, C => 
        \DWACT_ADD_CI_0_pog_array_1_5[0]\, Y => G_1_3_0);
    
    \dataout[20]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_23\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[20]\);
    
    \ad_4[0]\ : AND2
      port map(A => \ad_temp[0]_net_1\, B => \cur_state[7]_net_1\, 
        Y => \ad_4[0]_net_1\);
    
    datain_temp_73 : MUX2H
      port map(A => \datain_temp[21]_net_1\, B => 
        data_connect(21), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_73\);
    
    datain_temp_80 : MUX2H
      port map(A => \datain_temp[28]_net_1\, B => 
        data_connect(28), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_80\);
    
    un1_cur_state_i_a2 : NOR2
      port map(A => \cur_state[2]_net_1\, B => 
        \cur_state[6]_net_1\, Y => \un1_cur_state_i_a2\);
    
    \cur_state[8]\ : DFFS
      port map(CLK => inclk_c, D => \cur_state_ns[0]\, SET =>