connect.vhd

fpga从FIFO读数据并上传到双口ram中。

    un1_ad_temp_2_G_1_0_2 : AND3
      port map(A => G_1_0_1_1, B => \ad_temp[0]_net_1\, C => 
        \ad_temp[1]_net_1\, Y => G_1_0_2);
    
    \dataout_4[5]\ : MUX2H
      port map(A => \data_temp[1]_net_1\, B => 
        \datain_temp[5]_net_1\, S => \cur_state[6]_net_1\, Y => 
        \dataout_4[5]_net_1\);
    
    datain_temp_67 : MUX2H
      port map(A => \datain_temp[15]_net_1\, B => 
        data_connect(15), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_67\);
    
    \ad[2]\ : DFFC
      port map(CLK => inclk_c, D => \ad_37\, CLR => 
        inrst_c_i_0_13, Q => \ads_c[2]\);
    
    dataout_17 : MUX2H
      port map(A => \dataout_4[14]_net_1\, B => \dataouts_c[14]\, 
        S => N_230_1, Y => \dataout_17\);
    
    \ad_temp[9]\ : DFFC
      port map(CLK => inclk_c, D => \ad_temp_6[9]\, CLR => 
        inrst_c_i_0_17, Q => \ad_temp[9]_net_1\);
    
    \data_temp[0]\ : DFFC
      port map(CLK => inclk_c, D => \data_temp_50\, CLR => 
        inrst_c_i_0_13, Q => \data_temp[0]_net_1\);
    
    \ad_temp[12]\ : DFFC
      port map(CLK => inclk_c, D => I_55, CLR => inrst_c_i_0, Q
         => \ad_temp[12]_net_1\);
    
    ad_47 : MUX2H
      port map(A => \ad_4[12]_net_1\, B => \ads_c[12]\, S => 
        N_229_0, Y => \ad_47\);
    
    G_3_0_i_a3 : OR3
      port map(A => N_26_i, B => G_2_0_2_i, C => \G_2_1\, Y => 
        \G_3_0_i_a3\);
    
    datain_temp_61 : MUX2H
      port map(A => \datain_temp[9]_net_1\, B => data_connect(9), 
        S => \cur_state_2[7]_net_1\, Y => \datain_temp_61\);
    
    ad_40 : MUX2H
      port map(A => \ad_4[5]_net_1\, B => \ads_c[5]\, S => 
        \un1_cur_state_2_i_a2\, Y => \ad_40\);
    
    \dataout_4[3]\ : MUX2H
      port map(A => \data_temp[1]_net_1\, B => 
        \datain_temp[3]_net_1\, S => \cur_state[6]_net_1\, Y => 
        \dataout_4[3]_net_1\);
    
    \dataout[29]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_32\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[29]\);
    
    \cur_state_1[6]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state[7]_net_1\, CLR => 
        inrst_c_i_0_9_0, Q => \cur_state_1[6]_net_1\);
    
    ad_temp_0_sqmuxa_10 : NAND3
      port map(A => \ad_temp_0_sqmuxa_6\, B => \ad_temp[0]_net_1\, 
        C => \ad_temp[1]_net_1\, Y => ad_temp_0_sqmuxa_10_i);
    
    un1_cur_state_1_i_a2 : OR2
      port map(A => \cur_state[1]_net_1\, B => 
        \cur_state[5]_net_1\, Y => \un1_cur_state_1_i_a2\);
    
    \ad_temp_i_0_0[14]\ : INV
      port map(A => inrst_c, Y => inrst_c_i_0_0);
    
    dataout_23 : MUX2H
      port map(A => \dataout_4[20]_net_1\, B => \dataouts_c[20]\, 
        S => N_230_0, Y => \dataout_23\);
    
    un1_ad_temp_2_G_1_0_1_0 : AND3
      port map(A => \DWACT_ADD_CI_0_pog_array_2[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_2_1[0]\, C => 
        \ad_temp[12]_net_1\, Y => G_1_0_1_0);
    
    \dataout_4[7]\ : MUX2H
      port map(A => \data_temp[1]_net_1\, B => 
        \datain_temp[7]_net_1\, S => \cur_state[6]_net_1\, Y => 
        \dataout_4[7]_net_1\);
    
    \datain_temp[25]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_77\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[25]_net_1\);
    
    un1_ad_temp_2_G_1_0_0_0 : NAND2
      port map(A => \DWACT_ADD_CI_0_pog_array_2[0]\, B => 
        \ad_temp[8]_net_1\, Y => G_1_0_0_i);
    
    \cur_state_ns_0_a2[0]\ : NAND2FT
      port map(A => comuni_connect, B => \cur_state[8]_net_1\, Y
         => \cur_state_ns_0_a2[0]_net_1\);
    
    ad_tt_1_84 : OR2
      port map(A => \ad_tt_0[1]_net_1\, B => ad_tt_0_sqmuxa, Y
         => \ad_tt_1_84\);
    
    ad_temp_0_sqmuxa_4 : NOR2FT
      port map(A => \ad_temp[11]_net_1\, B => \ad_temp[4]_net_1\, 
        Y => \ad_temp_0_sqmuxa_4\);
    
    un1_ad_temp_2_G_1_6 : NAND3
      port map(A => \G_1_0_0\, B => G_1_0_0_1, C => \G_0\, Y => 
        G_1_6);
    
    \cur_state[2]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state[3]_net_1\, CLR => 
        inrst_c_i_0_10, Q => \cur_state[2]_net_1\);
    
    \dataout[10]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_13\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[10]\);
    
    \datain_temp[13]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_65\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[13]_net_1\);
    
    dataout_13 : MUX2H
      port map(A => \dataout_4[10]_net_1\, B => \dataouts_c[10]\, 
        S => N_230_1, Y => \dataout_13\);
    
    \dataout[6]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_9\, CLR => 
        inrst_c_i_0_14, Q => \dataouts_c[6]\);
    
    datain_temp_82 : MUX2H
      port map(A => \datain_temp[30]_net_1\, B => 
        data_connect(30), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_82\);
    
    \ad_temp[2]\ : DFFC
      port map(CLK => inclk_c, D => I_52, CLR => inrst_c_i_0_17, 
        Q => \ad_temp[2]_net_1\);
    
    G_3_0_i : AND2
      port map(A => \G_3_0_i_a3\, B => \G_2\, Y => \G_3_0_i\);
    
    \ad[10]\ : DFFC
      port map(CLK => inclk_c, D => \ad_45\, CLR => 
        inrst_c_i_0_14, Q => \ads_c[10]\);
    
    un1_ad_temp_2_I_85 : AND2
      port map(A => \ad_temp[2]_net_1\, B => \ad_temp[3]_net_1\, 
        Y => \DWACT_ADD_CI_0_pog_array_1[0]\);
    
    \cur_state[5]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state[6]_net_1\, CLR => 
        inrst_c_i_0_9_0, Q => \cur_state[5]_net_1\);
    
    datain_temp_56 : MUX2H
      port map(A => \datain_temp[4]_net_1\, B => data_connect(4), 
        S => \cur_state_2[7]_net_1\, Y => \datain_temp_56\);
    
    un1_ad_temp_2_I_89 : AND2
      port map(A => \ad_temp[8]_net_1\, B => \ad_temp[9]_net_1\, 
        Y => \DWACT_ADD_CI_0_pog_array_1_3[0]\);
    
    G_1_4 : OR2
      port map(A => \ad_temp[12]_net_1\, B => \ad_temp[13]_net_1\, 
        Y => un9_ad_temp_7_i_i);
    
    \ad_temp_i_0_1_0[14]\ : INV
      port map(A => inrst_c_0, Y => inrst_c_i_0_1_0);
    
    un1_ad_temp_2_G_1_4 : AND2
      port map(A => \G_1_0_0\, B => \ad_temp[0]_net_1\, Y => 
        \DWACT_ADD_CI_0_TMP[0]\);
    
    G_0 : OR2
      port map(A => \ad_temp[3]_net_1\, B => \ad_temp[14]_net_1\, 
        Y => G_0_i);
    
    \ad[4]\ : DFFC
      port map(CLK => inclk_c, D => \ad_39\, CLR => 
        inrst_c_i_0_13_0, Q => \ads_c[4]\);
    
    \ad_temp_i_0_8[14]\ : INV
      port map(A => inrst_c, Y => inrst_c_i_0_8);
    
    G_2_1 : OR3
      port map(A => \G_2_2_0\, B => un9_ad_temp_7_i_i, C => 
        \ad_temp[14]_net_1\, Y => \G_2_1\);
    
    \datain_temp[26]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_78\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[26]_net_1\);
    
    un1_ad_temp_2_G_1 : AND2
      port map(A => \DWACT_ADD_CI_0_pog_array_2[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_2_1[0]\, Y => \G_1\);
    
    G_2_2 : OR3
      port map(A => G_2_2_0_0, B => \ad_temp[8]_net_1\, C => 
        \ad_temp_i_0_i[6]\, Y => \G_2_2_0\);
    
    \dataout_4[28]\ : MUX2H
      port map(A => \data_temp_0[1]_net_1\, B => 
        \datain_temp[28]_net_1\, S => \cur_state_0[6]_net_1\, Y
         => \dataout_4[28]_net_1\);
    
    datain_temp_60 : MUX2H
      port map(A => \datain_temp[8]_net_1\, B => data_connect(8), 
        S => \cur_state_2[7]_net_1\, Y => \datain_temp_60\);
    
    \datain_temp[4]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_56\, CLR => 
        inrst_c_i_0_10, Q => \datain_temp[4]_net_1\);
    
    ad_44 : MUX2H
      port map(A => \ad_4[9]_net_1\, B => \ads_c[9]\, S => 
        N_229_0, Y => \ad_44\);
    
    un1_ad_temp_2_G_1_1_2 : XOR2
      port map(A => \ad_temp[5]_net_1\, B => G_1_6, Y => 
        \un1_ad_temp_2_i[6]\);
    
    \datain_temp[22]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_74\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[22]_net_1\);
    
    \ad_temp_i_0_13[14]\ : INV
      port map(A => inrst_c_0, Y => inrst_c_i_0_13);
    
    \data_temp[1]\ : DFFC
      port map(CLK => inclk_c, D => \data_temp_51\, CLR => 
        inrst_c_i_0_13, Q => \data_temp[1]_net_1\);
    
    PWR_i : PWR
      port map(Y => \VCC\);
    
    G_4 : OR3
      port map(A => \G_3_0\, B => G_0_i, C => \ad_temp[4]_net_1\, 
        Y => G_4_i);
    
    \dataout_4[23]\ : MUX2H
      port map(A => \data_temp_0[1]_net_1\, B => 
        \datain_temp[23]_net_1\, S => \cur_state_0[6]_net_1\, Y
         => \dataout_4[23]_net_1\);
    
    datain_temp_83 : MUX2H
      port map(A => \datain_temp[31]_net_1\, B => 
        data_connect(31), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_83\);
    
    dataout_4 : MUX2H
      port map(A => \dataout_4[1]_net_1\, B => \dataouts_c[1]\, S
         => \un1_cur_state_i_a2\, Y => \dataout_4\);
    
    \datain_temp[9]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_61\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[9]_net_1\);
    
    \ad_temp[3]\ : DFFC
      port map(CLK => inclk_c, D => G_5, CLR => inrst_c_i_0_17, Q
         => \ad_temp[3]_net_1\);
    
    \datain_temp[31]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_83\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[31]_net_1\);
    
    \dataout[5]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_8\, CLR => 
        inrst_c_i_0_14, Q => \dataouts_c[5]\);
    
    G : AND2FT
      port map(A => \un1_ad_temp_2_i[8]\, B => 
        ad_temp_0_sqmuxa_i_0, Y => \ad_temp_6[7]\);
    
    datain_temp_78 : MUX2H
      port map(A => \datain_temp[26]_net_1\, B => 
        data_connect(26), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_78\);
    
    un1_cur_state_i_a2_1 : NOR2
      port map(A => \cur_state[2]_net_1\, B => 
        \cur_state_0[6]_net_1\, Y => N_230_1);
    
    un1_cur_state_i_a2_0 : NOR2
      port map(A => \cur_state[2]_net_1\, B => 
        \cur_state_0[6]_net_1\, Y => N_230_0);
    
    \cur_state[4]\ : DFFC
      port map(CLK => inclk_c, D => ad_tt_0_sqmuxa, CLR => 
        inrst_c_i_0_9_0, Q => \cur_state[4]_net_1\);
    
    \cur_state_ns_0_a2[4]\ : AND2FT
      port map(A => \G_3_0_i\, B => \cur_state[5]_net_1\, Y => 
        ad_tt_0_sqmuxa);
    
    dataout_33 : MUX2H
      port map(A => \dataout_4[30]_net_1\, B => \dataouts_c[30]\, 
        S => N_230_0, Y => dataout_33_0);
    
    \cur_state[1]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state[2]_net_1\, CLR => 
        inrst_c_i_0_10, Q => \cur_state[1]_net_1\);
    
    un1_ad_temp_2_G_1_3 : XOR2FT
      port map(A => \ad_temp[11]_net_1\, B => \G_1_2_0\, Y => 
        \un1_ad_temp_2_i[12]\);
    
    \datain_temp[17]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_69\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[17]_net_1\);
    
    datain_temp_66 : MUX2H
      port map(A => \datain_temp[14]_net_1\, B => 
        data_connect(14), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_66\);
    
    \dataout_4[17]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[17]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[17]_net_1\);
    
    datain_temp_59 : MUX2H
      port map(A => \datain_temp[7]_net_1\, B => data_connect(7), 
        S => \cur_state_2[7]_net_1\, Y => \datain_temp_59\);
    
    G_3_0 : OR3
      port map(A => G_1_i, B => \ad_temp[11]_net_1\, C => 
        \ad_temp[13]_net_1\, Y => \G_3_0\);
    
    \datain_temp[2]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_54\, CLR => 
        inrst_c_i_0_10, Q => \datain_temp[2]_net_1\);
    
    datain_temp_74 : MUX2H
      port map(A => \datain_temp[22]_net_1\, B => 
        data_connect(22), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_74\);
    
    \cur_state_3[7]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state_ns[1]\, CLR => 
        inrst_c_i_0_9_0, Q => \cur_state_3[7]_net_1\);
    
    \dataout_4[14]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[14]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[14]_net_1\);
    
    \ad_temp[13]\ : DFFC
      port map(CLK => inclk_c, D => G_1_2_1, CLR => inrst_c_i_0, 
        Q => \ad_temp[13]_net_1\);
    
    \dataout[7]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_10\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[7]\);
    
    G_2_1_1 : NAND3FTT
      port map(A => \G_2_2_0\, B => \ad_temp[2]_net_1\, C => 
        \ad_temp[9]_net_1\, Y => G_2_1_1_i);
    
    dataout_9 : MUX2H