connect.vhd

fpga从FIFO读数据并上传到双口ram中。

         => \dataout_4[24]_net_1\);
    
    \dataout[21]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_24\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[21]\);
    
    \dataout[22]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_25\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[22]\);
    
    \cur_state[0]\ : DFFS
      port map(CLK => inclk_c, D => \cur_state_i[1]_net_1\, SET
         => inrst_c_i_0_10, Q => \cur_state_i_0[0]\);
    
    un1_ad_temp_2_I_88 : AND2
      port map(A => \ad_temp[10]_net_1\, B => \ad_temp[11]_net_1\, 
        Y => \DWACT_ADD_CI_0_pog_array_1_4[0]\);
    
    datain_temp_70 : MUX2H
      port map(A => \datain_temp[18]_net_1\, B => 
        data_connect(18), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_70\);
    
    ad_37 : MUX2H
      port map(A => \ad_4[2]_net_1\, B => \ads_c[2]\, S => 
        \un1_cur_state_2_i_a2\, Y => \ad_37\);
    
    datain_temp_63 : MUX2H
      port map(A => \datain_temp[11]_net_1\, B => 
        data_connect(11), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_63\);
    
    \cur_state_ns_0[0]\ : NAND3
      port map(A => ad_tt_1_sqmuxa, B => 
        \cur_state_ns_0_a2[0]_net_1\, C => \cur_state_i_0[0]\, Y
         => \cur_state_ns[0]\);
    
    ad_46 : MUX2H
      port map(A => \ad_4[11]_net_1\, B => \ads_c[11]\, S => 
        N_229_0, Y => \ad_46\);
    
    ad_49 : MUX2H
      port map(A => \ad_4[14]_net_1\, B => \ads_c[14]\, S => 
        N_229_0, Y => \ad_49\);
    
    \datain_temp[23]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_75\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[23]_net_1\);
    
    datain_temp_65 : MUX2H
      port map(A => \datain_temp[13]_net_1\, B => 
        data_connect(13), S => \cur_state_1[7]_net_1\, Y => 
        \datain_temp_65\);
    
    un1_ad_temp_2_I_53 : XOR2
      port map(A => \ad_temp[4]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_2[0]\, Y => I_53);
    
    dataout_6 : MUX2H
      port map(A => \dataout_4[3]_net_1\, B => \dataouts_c[3]\, S
         => \un1_cur_state_i_a2\, Y => \dataout_6\);
    
    \dataout[23]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_26\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[23]\);
    
    rw : DFFS
      port map(CLK => inclk_c, D => \rw_2\, SET => 
        \inrst_c_i_0_9\, Q => \rws_c\);
    
    \data_temp_1[1]\ : DFFC
      port map(CLK => inclk_c, D => \data_temp_51\, CLR => 
        inrst_c_i_0_13_0, Q => \data_temp_1[1]_net_1\);
    
    datain_temp_76 : MUX2H
      port map(A => \datain_temp[24]_net_1\, B => 
        data_connect(24), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_76\);
    
    \dataout[0]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_3\, CLR => 
        inrst_c_i_0_14, Q => \dataouts_c[0]\);
    
    un1_ad_temp_2_G : AND3
      port map(A => \G_1_0_0\, B => \G_1_0_1\, C => \G_0\, Y => 
        \DWACT_ADD_CI_0_g_array_11[0]\);
    
    \dataout_4[8]\ : MUX2H
      port map(A => \data_temp[1]_net_1\, B => 
        \datain_temp[8]_net_1\, S => \cur_state[6]_net_1\, Y => 
        \dataout_4[8]_net_1\);
    
    \cur_state_0[7]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state_ns[1]\, CLR => 
        inrst_c_i_0_9_0, Q => \cur_state_0[7]_net_1\);
    
    \dataout[14]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_17\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[14]\);
    
    \dataout_4[15]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[15]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[15]_net_1\);
    
    \dataout[28]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_31\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[28]\);
    
    un1_ad_temp_2_G_5 : XOR2FT
      port map(A => \ad_temp[3]_net_1\, B => G_1_1_0, Y => G_5);
    
    dataout_24 : MUX2H
      port map(A => \dataout_4[21]_net_1\, B => \dataouts_c[21]\, 
        S => N_230_0, Y => \dataout_24\);
    
    \ad_4[9]\ : MUX2H
      port map(A => \ad_tt_0[1]_net_1\, B => \ad_temp[9]_net_1\, 
        S => \cur_state_3[7]_net_1\, Y => \ad_4[9]_net_1\);
    
    \dataout_4[26]\ : MUX2H
      port map(A => \data_temp_0[1]_net_1\, B => 
        \datain_temp[26]_net_1\, S => \cur_state_0[6]_net_1\, Y
         => \dataout_4[26]_net_1\);
    
    dataout_28 : MUX2H
      port map(A => \dataout_4[25]_net_1\, B => \dataouts_c[25]\, 
        S => N_230_0, Y => \dataout_28\);
    
    \dataout[3]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_6\, CLR => 
        inrst_c_i_0_14, Q => \dataouts_c[3]\);
    
    \ad[3]\ : DFFC
      port map(CLK => inclk_c, D => \ad_38\, CLR => 
        inrst_c_i_0_13, Q => \ads_c[3]\);
    
    \ad_temp[7]\ : DFFC
      port map(CLK => inclk_c, D => \ad_temp_6[7]\, CLR => 
        inrst_c_i_0_17, Q => \ad_temp[7]_net_1\);
    
    G_2_0_0 : NAND2FT
      port map(A => un14_ad_temp_0_i, B => \ad_temp[3]_net_1\, Y
         => G_2_0_0_i);
    
    un14_ad_temp_0 : OR2
      port map(A => \ad_temp[11]_net_1\, B => \ad_temp[9]_net_1\, 
        Y => un14_ad_temp_0_i);
    
    un1_ad_temp_2_G_1_1_1 : AND3
      port map(A => \DWACT_ADD_CI_0_pog_array_1[0]\, B => 
        \ad_temp[0]_net_1\, C => \ad_temp[1]_net_1\, Y => \G_1_1\);
    
    \ad_4[8]\ : MUX2H
      port map(A => \ad_tt_0[1]_net_1\, B => \ad_temp[8]_net_1\, 
        S => \cur_state_3[7]_net_1\, Y => \ad_4[8]_net_1\);
    
    \datain_temp[5]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_57\, CLR => 
        inrst_c_i_0_10, Q => \datain_temp[5]_net_1\);
    
    \ad_temp_i_0_6[14]\ : INV
      port map(A => inrst_c, Y => inrst_c_i_0_6);
    
    dataout_14 : MUX2H
      port map(A => \dataout_4[11]_net_1\, B => \dataouts_c[11]\, 
        S => N_230_1, Y => \dataout_14\);
    
    \ad[0]\ : DFFC
      port map(CLK => inclk_c, D => \ad_35\, CLR => 
        inrst_c_i_0_13, Q => \ads_c[0]\);
    
    dataout_18 : MUX2H
      port map(A => \dataout_4[15]_net_1\, B => \dataouts_c[15]\, 
        S => N_230_1, Y => \dataout_18\);
    
    \ad_temp_i_0_16[14]\ : INV
      port map(A => inrst_c_0, Y => inrst_c_i_0_16);
    
    \ad_temp[1]\ : DFFC
      port map(CLK => inclk_c, D => I_56, CLR => inrst_c_i_0_17, 
        Q => \ad_temp[1]_net_1\);
    
    \ad_temp_i_0_17[14]\ : INV
      port map(A => inrst_c_0, Y => inrst_c_i_0_17);
    
    un1_ad_temp_2_G_1_2 : AND3
      port map(A => \G_1_0_0\, B => G_1_2_3, C => 
        \DWACT_ADD_CI_0_pog_array_2[0]\, Y => \G_1_2_0\);
    
    un1_ad_temp_2_G_1_0 : AND3
      port map(A => \G_1_0_0\, B => G_1_0_2, C => 
        \DWACT_ADD_CI_0_pog_array_2[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_11_1[0]\);
    
    \dataout_4[30]\ : MUX2H
      port map(A => \data_temp_0[1]_net_1\, B => 
        \datain_temp[30]_net_1\, S => \cur_state_0[6]_net_1\, Y
         => \dataout_4[30]_net_1\);
    
    \datain_temp[18]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_70\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[18]_net_1\);
    
    datain_temp_57 : MUX2H
      port map(A => \datain_temp[5]_net_1\, B => data_connect(5), 
        S => \cur_state_2[7]_net_1\, Y => \datain_temp_57\);
    
    \dataout_4[19]\ : MUX2H
      port map(A => \data_temp_1[1]_net_1\, B => 
        \datain_temp[19]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[19]_net_1\);
    
    dataout_5 : MUX2H
      port map(A => \dataout_4[2]_net_1\, B => \dataouts_c[2]\, S
         => \un1_cur_state_i_a2\, Y => \dataout_5\);
    
    \ad_4[10]\ : MUX2H
      port map(A => \ad_tt_0[1]_net_1\, B => \ad_temp[10]_net_1\, 
        S => \cur_state_3[7]_net_1\, Y => \ad_4[10]_net_1\);
    
    ad_43 : MUX2H
      port map(A => \ad_4[8]_net_1\, B => \ads_c[8]\, S => 
        N_229_0, Y => \ad_43\);
    
    un1_ad_temp_2_G_2_0 : AND3
      port map(A => \G_1_0_0\, B => \G_0\, C => 
        \DWACT_ADD_CI_0_pog_array_1[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_2[0]\);
    
    \dataout_4[9]\ : MUX2H
      port map(A => \data_temp[1]_net_1\, B => 
        \datain_temp[9]_net_1\, S => \cur_state[6]_net_1\, Y => 
        \dataout_4[9]_net_1\);
    
    \ad_temp_i_0_7[14]\ : INV
      port map(A => inrst_c, Y => inrst_c_i_0_7);
    
    \dataout_4[22]\ : MUX2H
      port map(A => \data_temp_0[1]_net_1\, B => 
        \datain_temp[22]_net_1\, S => \cur_state_0[6]_net_1\, Y
         => \dataout_4[22]_net_1\);
    
    \dataout[30]\ : DFFC
      port map(CLK => inclk_c, D => dataout_33_0, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[30]\);
    
    \datain_temp[27]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_79\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[27]_net_1\);
    
    \ad_temp_6[4]\ : AND2
      port map(A => ad_temp_0_sqmuxa_i_0, B => I_53, Y => 
        \ad_temp_6[4]_net_1\);
    
    un1_ad_temp_2_G_1_2_2 : AND3
      port map(A => \DWACT_ADD_CI_0_pog_array_1[0]\, B => 
        \ad_temp[1]_net_1\, C => \ad_temp[10]_net_1\, Y => 
        G_1_2_2);
    
    datain_temp_79 : MUX2H
      port map(A => \datain_temp[27]_net_1\, B => 
        data_connect(27), S => \cur_state_0[7]_net_1\, Y => 
        \datain_temp_79\);
    
    un1_ad_temp_2_G_2 : AND3
      port map(A => \G_1_0_0\, B => \G_1_1\, C => 
        \DWACT_ADD_CI_0_pog_array_2[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_3[0]\);
    
    \cur_state[6]\ : DFFC
      port map(CLK => inclk_c, D => \cur_state[7]_net_1\, CLR => 
        inrst_c_i_0_9_0, Q => \cur_state[6]_net_1\);
    
    \ad_4[13]\ : MUX2H
      port map(A => \ad_tt_0[1]_net_1\, B => \ad_temp[13]_net_1\, 
        S => \cur_state_3[7]_net_1\, Y => \ad_4[13]_net_1\);
    
    \ad_4[5]\ : MUX2H
      port map(A => \ad_tt[1]_net_1\, B => \ad_temp[5]_net_1\, S
         => \cur_state_3[7]_net_1\, Y => \ad_4[5]_net_1\);
    
    \ad[8]\ : DFFC
      port map(CLK => inclk_c, D => \ad_43\, CLR => 
        inrst_c_i_0_13_0, Q => \ads_c[8]\);
    
    dataout_7 : MUX2H
      port map(A => \dataout_4[4]_net_1\, B => \dataouts_c[4]\, S
         => \un1_cur_state_i_a2\, Y => \dataout_7\);
    
    \dataout_4[10]\ : MUX2H
      port map(A => \data_temp[1]_net_1\, B => 
        \datain_temp[10]_net_1\, S => \cur_state_1[6]_net_1\, Y
         => \dataout_4[10]_net_1\);
    
    \ad_temp_i_0_15[14]\ : INV
      port map(A => inrst_c_0, Y => inrst_c_i_0_15);
    
    un1_ad_temp_2_I_57 : XOR2
      port map(A => \ad_temp[8]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_3[0]\, Y => I_57);
    
    \datain_temp[14]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_66\, CLR => 
        inrst_c_i_0_11, Q => \datain_temp[14]_net_1\);
    
    un1_ad_temp_2_G_1_0_0_1 : AND2
      port map(A => \DWACT_ADD_CI_0_pog_array_1[0]\, B => 
        \ad_temp[4]_net_1\, Y => G_1_0_0_1);
    
    ad_temp_0_sqmuxa_3 : NAND2
      port map(A => \ad_temp[5]_net_1\, B => \ad_temp[7]_net_1\, 
        Y => ad_temp_0_sqmuxa_3_i);
    
    \datain_temp[6]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_58\, CLR => 
        inrst_c_i_0_10, Q => \datain_temp[6]_net_1\);
    
    ad_temp_0_sqmuxa_12 : OR3
      port map(A => ad_temp_0_sqmuxa_9_i, B => 
        ad_temp_0_sqmuxa_3_i, C => ad_temp_0_sqmuxa_1_i, Y => 
        ad_temp_0_sqmuxa_12_i);
    
    \dataout[17]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_20\, CLR => 
        inrst_c_i_0_15, Q => \dataouts_c[17]\);
    
    \ad[1]\ : DFFC
      port map(CLK => inclk_c, D => \ad_36\, CLR => 
        inrst_c_i_0_13, Q => \ads_c[1]\);
    
    dataout_27 : MUX2H
      port map(A => \dataout_4[24]_net_1\, B => \dataouts_c[24]\, 
        S => N_230_0, Y => \dataout_27\);
    
    un1_ad_temp_2_G_1_1 : NAND3
      port map(A => \G_1_0_0\, B => G_1_0_6, C => 
        \ad_temp[0]_net_1\, Y => G_1_1_0);
    
    GND_i : GND
      port map(Y => \GND\);
    
    \datain_temp[30]\ : DFFC
      port map(CLK => inclk_c, D => \datain_temp_82\, CLR => 
        inrst_c_i_0_12, Q => \datain_temp[30]_net_1\);
    
    \dataout[26]\ : DFFC
      port map(CLK => inclk_c, D => \dataout_29\, CLR => 
        inrst_c_i_0_16, Q => \dataouts_c[26]\);
    
    un1_ad_temp_2_G_2_2 : NAND3FTT
      port map(A => G_1_0_0_i, B => \G_1_0_0\, C => \G_1_1\, Y
         => \G_2_2\);
    
    dataout_34 : MUX2H
      port map(A => \dataout_4[31]_net_1\, B => \dataouts_c[31]\, 
        S => N_230_0, Y => dataout_34_0);
    
    \ad_temp_i_0_9_0[14]\ : INV
      port map(A => inrst_c_0, Y => inrst_c_i_0_9_0);