connect.srr

fpga从FIFO读数据并上传到双口ram中。

#Program: Synplify 8.1A
#OS: Windows_NT

$ Start of Compile
#Sat Mar 07 16:38:02 2009

Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@N:"C:\Actelprj\connect20090223\hdl\connect.vhd":7:7:7:13|Top entity is set to connect.
VHDL syntax check successful!
File C:\Actelprj\connect20090223\hdl\dpram_w.vhd changed - recompiling
@N:"C:\Actelprj\connect20090223\hdl\connect.vhd":6:7:6:13|Synthesizing work.connect.one 
@N:"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":9:7:9:13|Synthesizing work.dpram_w.one 
@N: CD231 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":33:11:33:12|Using onehot encoding for type state (s0="100000000")
Post processing for work.dpram_w.one
@W: CL190 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Optimizing register bit ad_tt(0) to a constant 0
@N: CL201 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Trying to extract state machine for register cur_state
Extracted state machine for register cur_state
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <14> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <13> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <12> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <11> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <10> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <9> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <8> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <7> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <6> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <5> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <4> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <3> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <2> of ad_tt(14 downto 1)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <31> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <30> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <29> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <28> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <27> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <26> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <25> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <24> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <23> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <22> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <21> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <20> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <19> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <18> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <17> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <16> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <15> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <14> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <13> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <12> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <11> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <10> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <9> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <8> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <7> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <6> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <5> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <4> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <3> of data_temp(31 downto 0)  
@W: CL171 :"C:\Actelprj\connect20090223\hdl\dpram_w.vhd":52:1:52:2|Pruning Register bit <2> of data_temp(31 downto 0)  
@N:"C:\Actelprj\connect20090223\hdl\fifo_r.vhd":7:7:7:12|Synthesizing work.fifo_r.one 
@N: CD231 :"C:\Actelprj\connect20090223\hdl\fifo_r.vhd":36:11:36:12|Using onehot encoding for type state (s0="100000000000")
Post processing for work.fifo_r.one
@N: CL201 :"C:\Actelprj\connect20090223\hdl\fifo_r.vhd":54:0:54:1|Trying to extract state machine for register cur_state
Extracted state machine for register cur_state
State machine has 12 reachable states with original encodings of:
   000000000001
   000000000010
   000000000100
   000000001000
   000000010000
   000000100000
   000001000000
   000010000000
   000100000000
   001000000000
   010000000000
   100000000000
Post processing for work.connect.one
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Mar 07 16:38:05 2009

###########################################################[
Version 8.1A
Synplicity Proasic Technology Mapper, Version 8.1.0, Build 006R, Built May 19 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved


RTL optimization done.
Encoding state machine work.fifo_r(one)-cur_state[0:11]
original code -> new code
   000000000001 -> 000000000001
   000000000010 -> 000000000010
   000000000100 -> 000000000100
   000000001000 -> 000000001000
   000000010000 -> 000000010000
   000000100000 -> 000000100000
   000001000000 -> 000001000000
   000010000000 -> 000010000000
   000100000000 -> 000100000000
   001000000000 -> 001000000000
   010000000000 -> 010000000000
   100000000000 -> 100000000000
Encoding state machine work.dpram_w(one)-cur_state[0:8]
original code -> new code
   000000001 -> 000000001
   000000010 -> 000000010
   000000100 -> 000000100
   000001000 -> 000001000
   000010000 -> 000010000
   000100000 -> 000100000
   001000000 -> 001000000
   010000000 -> 010000000
   100000000 -> 100000000
Promoting Net inclk_c on GL33  inclk_pad
Replicating inrst_c_i_0, fanout 220 segments 19
Replicating fiforr.cur_state[0], fanout 35 segments 3
Replicating fiforr.cur_state[2], fanout 36 segments 3
Replicating dpram.N_230, fanout 33 segments 3
Replicating dpram.N_229, fanout 16 segments 2
Replicating dpram.ad_tt[1], fanout 15 segments 2
Replicating dpram.data_temp[1], fanout 32 segments 3
Replicating dpram.cur_state[7], fanout 50 segments 5
Replicating dpram.cur_state[6], fanout 36 segments 3
Replicating inrst_c_i_0_13, fanout 14 segments 2
Replicating inrst_c_i_0_9, fanout 19 segments 2
Replicating inrst_c_i_0_1, fanout 16 segments 2
Buffering inrst_c, fanout 22 segments 2

Added 1 Buffers
Added 37 Cells via replication
Writing Analyst data base C:\Actelprj\connect20090223\synthesis\connect.srm
Writing EDIF Netlist and constraint files
Found clock connect|inclk with period 10.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Sat Mar 07 16:38:10 2009
#


Top view:               connect
Library name:           APA
Operating conditions:   TYPICAL ( T = 25.0, V = 2.50, P = 1.00, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        APA
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -6.300

                   Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
----------------------------------------------------------------------------------------------------------------------
connect|inclk      100.0 MHz     61.4 MHz      10.000        16.300        -6.300     inferred     Inferred_clkgroup_0
======================================================================================================================