connect20090223.prj

fpga从FIFO读数据并上传到双口ram中。

KEY LIBERO "6.2"
KEY CAPTURE "6.2.50.1"
KEY HDLTechnology "VHDL"
KEY VendorTechnology_Family "PA"
KEY VendorTechnology_Die "150"
KEY VendorTechnology_Package "pq208"
KEY ProjectLocation "C:\Actelprj\connect20090223"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "connect"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST PackageFiles
ENDLIST
LIST BlockSymbols
ENDLIST
LIST Schematics
ENDLIST
LIST HDLFiles
VALUE "hdl\connect.vhd"
VALUE "hdl\dpram_w.vhd"
VALUE "hdl\fifo_r.vhd"
ENDLIST
LIST GENFiles
ENDLIST
LIST SynthesisFiles
VALUE "synthesis\connect.edn"
VALUE "synthesis\connect.vhd"
VALUE "synthesis\connect_sdc.sdc"
ENDLIST
LIST PhySynthesisFiles
ENDLIST
LIST StimulusFiles
VALUE "stimulus\testbench.vhd"
ENDLIST
LIST ConstraintFiles
ENDLIST
LIST RecentFile
ENDLIST
LIST StimulusAssociation
LIST connect
testbench.vhd
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=TRUE
CompilePackage=TRUE
IncludeWaveDo=FALSE
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
Profile=ModelSim
Tool=ModelSim
Location=C:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
Batch=FALSE
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=TRUE
GenerateHDLAfterPhySynthesis=TRUE
ENDLIST
LIST StimulusOptions
Profile=WFL
Tool=WFL
Location=C:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
Batch=FALSE
ENDLIST
LIST SynthesisOptions
Profile=Synplify_1
Tool=Synplify
Location=C:\Libero\Synplify\Synplify_81A\bin\Synplify.exe
AdditionalParameter=
Batch=FALSE
ENDLIST
LIST PhySynthesisOptions
Profile=PALACE
Tool=PALACE
Location=C:\Libero\PALACE\bin\palace_actel.exe
AdditionalParameter=
Batch=FALSE
ENDLIST
LIST ProjectState5.1
LIST "connect"
LIST Impl1
LiberoState=Post_Synthesis
ideSYNTHESIS=StateSuccess
ideSTIMULUS=StateSuccess
LIST Files Up To Date
connect.edn
connect_sdc.sdc
connect.vhd
ENDLIST
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
ENDLIST
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST OODAdbs
ENDLIST