testbench.vhd

fpga从FIFO读数据并上传到双口ram中。

--testbench.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity testbench is
end entity;

architecture one of testbench is
component connect is
port( inclk: in std_logic;
      inrst: in std_logic;
--fifo
      ffs :    in  std_logic; 
      hfs:    in  std_logic;
      datains:   in  std_logic_vector(7 downto 0); 

      sc_ds:   in  std_logic;--data or control data
      rdys:    in   std_logic;
 
      bstns :  out std_logic;--set 1 the 8\10b trans
      rfs:     out  std_logic; --reframe ,set 1 to find k28.5
      fifows:    out std_logic; --write enable
      fifors :   out std_logic;
      mrs:       out std_logic;--mr

--dpram
      dataouts: out std_logic_vector(31 downto 0);
   
      ads: out std_logic_vector(14 downto 0);
      ces: out std_logic;
      rws : out std_logic;

      oes: out std_logic;
      bms:  out std_logic;
      sizes:  out std_logic;
      semps: out std_logic);
end component;

signal      inclk:  std_logic;
signal      inrst:  std_logic;
--fifo
signal      ffs :      std_logic; 
signal      hfs:    std_logic;
signal      datains:     std_logic_vector(7 downto 0); 
signal      sc_ds:   std_logic;--data or control data
signal      rdys:       std_logic;
 
signal      bstns :  std_logic;--set 1 the 8\10b trans
signal      rfs:      std_logic; --reframe ,set 1 to find k28.5
signal      fifows:     std_logic; --write enable
signal      fifors :   std_logic;
signal      mrs:        std_logic;--mr

--dpram
signal      dataouts:  std_logic_vector(31 downto 0);
   
signal      ads:  std_logic_vector(14 downto 0);
signal      ces:  std_logic;
signal      rws :  std_logic;

signal      oes:  std_logic;
signal      bms:   std_logic;
signal      sizes:   std_logic;
signal      semps:  std_logic;

begin

gg:connect port map(inclk,inrst,ffs,hfs,datains,sc_ds,rdys,bstns,rfs,fifows,fifors,mrs,dataouts,ads,ces,rws,oes,bms,sizes,semps);

process begin
inclk<='1';wait for 18.5 ns;
inclk<='0';wait for 18.5 ns;
end process;

process begin
inrst<='1';wait for 30 ns;
inrst<='0';wait for 30 ns;
inrst<='1';wait;
end process;


process begin
hfs<='1';wait for 500 ns;
hfs<='0';wait for 30 ns;
end process;

process
begin
rdys<='1';wait for 25 ns;
rdys<='0';wait for 25 ns;
end process;

process
begin
sc_ds<='1';wait for 30 ns;
sc_ds<='0';wait for 30 ns;
end process;

process begin
ffs<='1';wait for 500 ns;
ffs<='0';wait for 30 ns;
ffs<='1';wait;
end process;

 process begin
datains <= x"01";
wait for 300 ns;
datains <= x"47";
wait until fifors = '1';
datains<=x"47";
wait until fifors='1';
datains<=x"47";
wait until fifors='1';
datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";
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datains<=x"47";