modelsim.ini

来自「fpga从FIFO读数据并上传到双口ram中。」· INI 代码 · 共 9 行

[Library]
others = $MODEL_TECH/../modelsim.ini
apa = C:/Libero/Model/actel/VHDL/apa
postsynth = ../simulation/postsynth
presynth = ../simulation/presynth
syncad_vhdl_lib = C:\Libero\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHDL93 = 1