watch.vhd

运用VHDL语言编写的秒表程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity watch is
port(sel:out std_logic_vector(6 downto 1);
seg:out std_logic_vector(7 downto 0);
beginstop:in std_logic;
reset:in std_logic;
qq:out std_logic;
cp2:in std_logic);
end watch;
architecture behave of watch is 
signal num1:std_logic_vector(3 downto 0);--秒计数个位
signal num2:std_logic_vector(3 downto 0);--秒计数十位
signal num3:std_logic_vector(3 downto 0);--分计数个位
signal num4:std_logic_vector(3 downto 0);--分计数十位
signal num5:std_logic_vector(3 downto 0);--时计数个位
signal num6:std_logic_vector(3 downto 0);--时计数十位
signal num:std_logic_vector(3 downto 0);
signal numlet:std_logic_vector(2 downto 0);
signal count:std_logic_vector(22 downto 1);
signal selsig:std_logic_vector(6 downto 1);
signal segsig:std_logic_vector(7 downto 0);
signal cp1:std_logic;
signal cp3:std_logic;
signal beginstop1:std_logic;
begin
process(cp2) --分频
begin
if(cp2'event and cp2='1')then
if(count=20000)then
count<="0000000000000000000000";
cp1<=not cp1;
else count<=count+1;
end if;
end if;
cp3<=count(10);
end process;
process(cp3)
begin
if(beginstop'event and beginstop='0')then 
beginstop1<=not beginstop1;
end if;
end process;
process(cp1,beginstop1)  --记时控制
begin
if reset='0' then num1(3 downto 0)<="0000";
                  num2(3 downto 0)<="0000";
                  num3(3 downto 0)<="0000";
                  num4(3 downto 0)<="0000";
                  num5(3 downto 0)<="0000";
                  num6(3 downto 0)<="0000";     
else if cp1'event and cp1='1' then
if beginstop1='1' then 
num1<=num1+1;
end if;
if num1(3 downto 0)="1001"then
num1(3 downto 0)<="0000";num2<=num2+1;
end if;
if num2(3 downto 0)="1001"then
num2(3 downto 0)<="0000";num3<=num3+1;
if num3(3 downto 0)="1001"then
num3(3 downto 0)<="0000";num4<=num4+1;
if num4(3 downto 0)="0101"then
num4(3 downto 0)<="0000";num5<=num5+1;
if num5(3 downto 0)="1001"then
num5(3 downto 0)<="0000";num6<=num6+1;
if num6(3 downto 0)="0101"then
num6(3 downto 0)<="0000";
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
process(cp3)   --动态显示部分
begin
if (cp3'event and cp3='1')then
numlet(2 downto 0)<="000";
if(numlet(2 downto 0)="000")then
num<=num1;selsig(6 downto 1)<="000001";qq<='0';
end if;
if(numlet(2 downto 0)="001")then
num<=num2;selsig(6 downto 1)<="000010";qq<='1';
end if;
if(numlet(2 downto 0)="010")then
num<=num3;selsig(6 downto 1)<="000100";qq<='0';
end if;
if(numlet(2 downto 0)="011")then
num<=num4;selsig(6 downto 1)<="001000";qq<='1';
end if;
if(numlet(2 downto 0)="100")then
num<=num5;selsig(6 downto 1)<="010000";qq<='0';
end if;
numlet(2 downto 0)<=numlet(2 downto 0)+"001";
if(numlet(2 downto 0)="101")then
num<=num6;selsig(6 downto 1)<="100000";qq<='0';
end if;
end if;
if(num(3 downto 0)="0000")then
segsig(7 downto 0)<="00111111";
end if;
if(num(3 downto 0)="0001")then
segsig(7 downto 0)<="00000110";
end if;
if(num(3 downto 0)="0010")then
segsig(7 downto 0)<="01011011";
end if;
if(num(3 downto 0)="0011")then
segsig(7 downto 0)<="01001111";
end if;
if(num(3 downto 0)="0100")then
segsig(7 downto 0)<="01100110";
end if;
if(num(3 downto 0)="0101")then
segsig(7 downto 0)<="01101101";
end if;
if(num(3 downto 0)="0110")then
segsig(7 downto 0)<="01111101";
end if;
if(num(3 downto 0)="0111")then
segsig(7 downto 0)<="00000111";
end if;
if(num(3 downto 0)="1000")then
segsig(7 downto 0)<="01111111";
end if;
if(num(3 downto 0)="1001")then
segsig(7 downto 0)<="01100111";
end if;
end process;
sel<=selsig(6 downto 1);
seg(7 downto 0)<=segsig(7 downto 0);
end behave;