clk4.map.summary

clk4 时钟分频设计用于FPGA入门设计

Analysis & Elaboration Status : Failed - Tue Feb 24 20:25:08 2009
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Web Edition
Revision Name : clk4
Top-level Entity Name : clk4
Family : Cyclone
Total logic elements : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
Total PLLs : N/A until Partition Merge