clk4.v.bak

来自「clk4 时钟分频设计用于FPGA入门设计」· BAK 代码 · 共 16 行

module freq3_027M(clkin12_288M, clkout3_027M); 
input clkin12_288M; //时钟输入引脚
output clkout3_027M; //时钟输出引脚
reg clkout3_027M; //分频计数器 
integer cunt; 
always@( posedge clkin12_288M) begin 
cunt=cunt+1; 
if (cunt<=1) 
begin clkout3_027M=1'b0;end
else if((cunt<=3)&&(cunt>=2))
begin clkout3_027M=1'b1;end
else 
begin cunt="0";clkout3_027M=1'b0;end
end
endmodule