ccd_dr.map.summary

verilog HDL语言

Analysis & Synthesis Status : Successful - Tue Jul 01 21:23:16 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : ccd_dr
Top-level Entity Name : ccd_dr
Family : MAX7000AE
Total macrocells : 30
Total pins : 28