prev_cmp_sram_test.tan.qmsg

来自「Verilog语言对SRAM的操作,也提一些简单的快速操作SRAM的技巧。」· QMSG 代码 · 共 14 行 · 第 1/3 页

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 26 -1 0 } } { "c:/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register delay\[18\] register addr_r\[8\] 79.03 MHz 12.653 ns Internal " "Info: Clock \"clk\" has Internal fmax of 79.03 MHz between source register \"delay\[18\]\" and destination register \"addr_r\[8\]\" (period= 12.653 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.944 ns + Longest register register " "Info: + Longest register to register delay is 11.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns delay\[18\] 1 REG LC_X5_Y3_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N6; Fanout = 4; REG Node = 'delay\[18\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { delay[18] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.887 ns) + CELL(0.914 ns) 1.801 ns Equal0~203 2 COMB LC_X5_Y3_N9 1 " "Info: 2: + IC(0.887 ns) + CELL(0.914 ns) = 1.801 ns; Loc. = LC_X5_Y3_N9; Fanout = 1; COMB Node = 'Equal0~203'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.801 ns" { delay[18] Equal0~203 } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.615 ns) + CELL(0.200 ns) 4.616 ns Equal0~206 3 COMB LC_X7_Y4_N8 2 " "Info: 3: + IC(2.615 ns) + CELL(0.200 ns) = 4.616 ns; Loc. = LC_X7_Y4_N8; Fanout = 2; COMB Node = 'Equal0~206'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.815 ns" { Equal0~203 Equal0~206 } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.200 ns) 6.816 ns Equal0~207 4 COMB LC_X7_Y1_N8 7 " "Info: 4: + IC(2.000 ns) + CELL(0.200 ns) = 6.816 ns; Loc. = LC_X7_Y1_N8; Fanout = 7; COMB Node = 'Equal0~207'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { Equal0~206 Equal0~207 } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 7.321 ns Equal1~114 5 COMB LC_X7_Y1_N9 3 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 7.321 ns; Loc. = LC_X7_Y1_N9; Fanout = 3; COMB Node = 'Equal1~114'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Equal0~207 Equal1~114 } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.200 ns) 8.245 ns Equal3~67 6 COMB LC_X7_Y1_N0 14 " "Info: 6: + IC(0.724 ns) + CELL(0.200 ns) = 8.245 ns; Loc. = LC_X7_Y1_N0; Fanout = 14; COMB Node = 'Equal3~67'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.924 ns" { Equal1~114 Equal3~67 } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.456 ns) + CELL(1.243 ns) 11.944 ns addr_r\[8\] 7 REG LC_X4_Y3_N0 4 " "Info: 7: + IC(2.456 ns) + CELL(1.243 ns) = 11.944 ns; Loc. = LC_X4_Y3_N0; Fanout = 4; REG Node = 'addr_r\[8\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.699 ns" { Equal3~67 addr_r[8] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.957 ns ( 24.76 % ) " "Info: Total cell delay = 2.957 ns ( 24.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.987 ns ( 75.24 % ) " "Info: Total interconnect delay = 8.987 ns ( 75.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "11.944 ns" { delay[18] Equal0~203 Equal0~206 Equal0~207 Equal1~114 Equal3~67 addr_r[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "11.944 ns" { delay[18] {} Equal0~203 {} Equal0~206 {} Equal0~207 {} Equal1~114 {} Equal3~67 {} addr_r[8] {} } { 0.000ns 0.887ns 2.615ns 2.000ns 0.305ns 0.724ns 2.456ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.200ns 0.200ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 59 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 59; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns addr_r\[8\] 2 REG LC_X4_Y3_N0 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y3_N0; Fanout = 4; REG Node = 'addr_r\[8\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk addr_r[8] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr_r[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} addr_r[8] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 59 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 59; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns delay\[18\] 2 REG LC_X5_Y3_N6 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N6; Fanout = 4; REG Node = 'delay\[18\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk delay[18] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk delay[18] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} delay[18] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr_r[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} addr_r[8] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk delay[18] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} delay[18] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "11.944 ns" { delay[18] Equal0~203 Equal0~206 Equal0~207 Equal1~114 Equal3~67 addr_r[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "11.944 ns" { delay[18] {} Equal0~203 {} Equal0~206 {} Equal0~207 {} Equal1~114 {} Equal3~67 {} addr_r[8] {} } { 0.000ns 0.887ns 2.615ns 2.000ns 0.305ns 0.724ns 2.456ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.200ns 0.200ns 1.243ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk addr_r[8] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} addr_r[8] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk delay[18] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} delay[18] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "rd_data\[0\] sram_data\[0\] clk 2.169 ns register " "Info: tsu for register \"rd_data\[0\]\" (data pin = \"sram_data\[0\]\", clock pin = \"clk\") is 2.169 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.184 ns + Longest pin register " "Info: + Longest pin to register delay is 5.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sram_data\[0\] 1 PIN PIN_54 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_54; Fanout = 1; PIN Node = 'sram_data\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sram_data[0] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sram_data\[0\]~15 2 COMB IOC_X8_Y1_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X8_Y1_N2; Fanout = 1; COMB Node = 'sram_data\[0\]~15'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { sram_data[0] sram_data[0]~15 } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.772 ns) + CELL(0.280 ns) 5.184 ns rd_data\[0\] 3 REG LC_X7_Y3_N9 1 " "Info: 3: + IC(3.772 ns) + CELL(0.280 ns) = 5.184 ns; Loc. = LC_X7_Y3_N9; Fanout = 1; REG Node = 'rd_data\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.052 ns" { sram_data[0]~15 rd_data[0] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 27.24 % ) " "Info: Total cell delay = 1.412 ns ( 27.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.772 ns ( 72.76 % ) " "Info: Total interconnect delay = 3.772 ns ( 72.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.184 ns" { sram_data[0] sram_data[0]~15 rd_data[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "5.184 ns" { sram_data[0] {} sram_data[0]~15 {} rd_data[0] {} } { 0.000ns 0.000ns 3.772ns } { 0.000ns 1.132ns 0.280ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 115 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 59 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 59; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns rd_data\[0\] 2 REG LC_X7_Y3_N9 1 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y3_N9; Fanout = 1; REG Node = 'rd_data\[0\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk rd_data[0] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk rd_data[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} rd_data[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.184 ns" { sram_data[0] sram_data[0]~15 rd_data[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "5.184 ns" { sram_data[0] {} sram_data[0]~15 {} rd_data[0] {} } { 0.000ns 0.000ns 3.772ns } { 0.000ns 1.132ns 0.280ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk rd_data[0] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} rd_data[0] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk sram_data\[4\] wr_data\[4\] 9.288 ns register " "Info: tco from clock \"clk\" to destination pin \"sram_data\[4\]\" through register \"wr_data\[4\]\" is 9.288 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 59 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 59; CLK Node = 'clk'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns wr_data\[4\] 2 REG LC_X7_Y1_N4 7 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y1_N4; Fanout = 7; REG Node = 'wr_data\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk wr_data[4] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk wr_data[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} wr_data[4] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.564 ns + Longest register pin " "Info: + Longest register to pin delay is 5.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wr_data\[4\] 1 REG LC_X7_Y1_N4 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y1_N4; Fanout = 7; REG Node = 'wr_data\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_data[4] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.242 ns) + CELL(2.322 ns) 5.564 ns sram_data\[4\] 2 PIN PIN_48 0 " "Info: 2: + IC(3.242 ns) + CELL(2.322 ns) = 5.564 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'sram_data\[4\]'" {  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.564 ns" { wr_data[4] sram_data[4] } "NODE_NAME" } } { "sram_test.v" "" { Text "C:/franchiese/GR/实验例程备份/实验例程以及说明文档/11、读写SRAM/verilogsram/sram_test.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 41.73 % ) " "Info: Total cell delay = 2.322 ns ( 41.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.242 ns ( 58.27 % ) " "Info: Total interconnect delay = 3.242 ns ( 58.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.564 ns" { wr_data[4] sram_data[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "5.564 ns" { wr_data[4] {} sram_data[4] {} } { 0.000ns 3.242ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk wr_data[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} wr_data[4] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.564 ns" { wr_data[4] sram_data[4] } "NODE_NAME" } } { "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/81/quartus/bin/Technology_Viewer.qrui" "5.564 ns" { wr_data[4] {} sram_data[4] {} } { 0.000ns 3.242ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}